Static information storage and retrieval – Floating gate – Particular connection
Reexamination Certificate
2000-01-14
2001-07-24
Nelms, David (Department: 2818)
Static information storage and retrieval
Floating gate
Particular connection
C365S185110, C365S185050
Reexamination Certificate
active
06266274
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The invention lies in the semiconductor technology field. More specifically, the invention relates to a semiconductor memory having at least one non-volatile, dual-transistor memory cell which has the following features:
an N-channel selection transistor and an N-channel memory transistor;
the N-channel selection transistor has a selection gate and two selection channels, the selection gate being connected to a row line leading to the memory cell;
the N-channel memory transistor has a memory gate or a control gate and two memory channels;
a second memory channel and a first selection channel are connected to one another, the other memory channel or respectively the other selection channel being connected to a column line leading to the memory cell;
whereby the semiconductor memory has at least one transfer transistor with a first and a second transfer channel, and the first transfer channel is connected to the memory gate.
In the generic semiconductor memories, the individual transistors are implemented in FET technology on a semiconductor substrate. The memory transistor thereby has a floating gate, with the result that it can be programmed, by the application of suitable voltages to the channels and to the gate, in such a way that it can assume a desired state permanently or in a non-volatile fashion.
In order to read the memory cell, a memory channel and a selection channel are connected to one another, the other free memory channel or respectively the other free selection channel being connected to a column line leading to the memory cell. In this case, the selection transistor is driven in such a way that it turns on. If a current then flows in the event of a voltage being applied to the corresponding column line, then the memory transistor has been programmed to “conducting”, or written to, in a previous step. If no current flows in the event of the voltage being applied to the column line with the selection transistor turned on, then the memory transistor has been programmed to “nonconducting”, or erased, in a previous step.
EP 0317 443 A1 discloses a two-transistor memory cell comprising a selection transistor and a floating gate transistor. A special voltage is applied to the gate of the floating gate transistor for driving purposes.
In the case of the memories of the generic type, the fact that the voltages required for programming have to be generated with high technological complexity is particularly problematic. Furthermore, in the course of programming one memory cell, faults are frequently produced in other memory cells which are not currently selected for programming.
SUMMARY OF THE INVENTION
The object of the invention is to provide a semiconductor memory device with non-volatile two-transistor memory cells, which overcomes the above-noted deficiencies and disadvantages of the prior art devices and methods of this kind, and which allows programming of the semiconductor memory in a fault-free manner with little technological complexity.
With the above and other objects in view there is provided, in accordance with the invention, a semiconductor memory with at least one memory cell, comprising:
an N-channel selection transistor having a selection gate connected to the row line, a first selection channel connection connected to the column line and a second selection channel connection;
an N-channel memory transistor having a memory gate, a first memory channel connection connected to the second selection channel connection, and a second memory channel connection;
the semiconductor memory further includes at least one P-channel transfer transistor having a first transfer channel connection connected to the memory gate and a second transfer channel connection connected to the row line leading to the memory cell.
In other words, the objects of the invention are attained by virtue of the fact that the transfer transistor is designed as a P-channel transfer transistor, the second transfer channel, unlike in the prior art, not being connected to an external control gate voltage but rather to the row line leading to the memory cell.
The invention is based on the insight that in the case of the circuits of the generic type, it is necessary to overcome a threshold voltage loss in the transfer transistor, so that higher transfer gate voltages have had to be provided. This problem can be solved by designing the transfer transistor as a transistor with a reduced threshold voltage, but this has to be bought at the expense of increased technological complexity.
With the way in which the transfer transistor is designed and connected up according to the invention, a transfer gate threshold voltage no longer needs to be overcome in order to program the memory transistor, with the result that reliable programming is possible with little technological complexity.
The invention is furthermore based on the insight that the control gate voltage “floats” in an undefined freewheel in the memory cells that are not currently being driven, on account of the particular way in which the transfer transistor is connected up in the prior art, which can lead to capacitive overcoupling of the programming voltages. Such capacitive overcoupling no longer occurs in the memory cells of the semiconductor memory according to the invention, since each memory gate is at a defined state during the programming of the semiconductor memory according to the invention.
In the system according to the invention, a logic signal converted to high voltage can be applied to the transfer gate of the transfer transistor. For this purpose, it is expedient to use a logic signal which also drives the respective programming state of the memory cell. In this case, the provision of an inverter, which is complicated to produce, for driving the transfer gate is avoided due to the design of the transfer transistor as a P-channel transfer transistor, since a P-channel transfer transistor turns off when the gate is driven, and vice-versa. In principle, however, the transfer transistor with such an inverter can also be designed as an N-channel transfer transistor.
The arrangement according to the invention makes it possible, without any losses and without further special measures, for the full programming voltage to be switched via the channel of the transfer transistor to the memory gates.
It should be understood that the invention can also be realized with a memory in which the memory and selection transistors are designed as P-channel transistors if the transfer transistor is then designed as an N-channel transistor. However, such an arrangement is more uncommon, but may afford advantages if so-called “hole conduction” is desired for the transfer of charge carriers.
In accordance with an added feature of the invention, a control line is connected to the transfer gate for driving the transfer transistor via the control line.
In accordance with an additional feature of the invention, there is provided an N-channel discharge transistor having a discharge gate connected to the control line, and a first discharge channel connection connected to the memory gate.
In accordance with another feature of the invention, the N-channel discharge transistor has a second discharge channel connection connected to ground.
In this development of the invention the drive circuit has an N-channel discharge transistor, which has a discharge gate and a first and a second discharge channel, the first discharge channel being connected to the memory gate, the second discharge channel being connected to ground, and the discharge gate being connected to that control line via which the transfer transistor is driven.
Such a discharge transistor ensures, during the programming of the memory cell, that the memory gate is at a defined potential, in particular at ground potential, during a programming operation. It is precisely when the transfer transistor is turned off that it is thereby ensured that the memory gate is at a potential of 0 V in a defined manner.
In accordance with a further feature of the inve
Pockrandt Wolfgang
Sedlak Holger
Viehmann Hans-Heinrich
Greenberg Laurence A.
Infineon - Technologies AG
Lam David
Lerner Herbert L.
Nelms David
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