Programmable low noise CMOS differentially voltage...

Miscellaneous active electrical nonlinear devices – circuits – and – Specific input to output function – Logarithmic

Reexamination Certificate

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C327S350000, C327S308000

Reexamination Certificate

active

06229375

ABSTRACT:

BACKGROUND OF THE INVENTION
The invention relates to variable gain logarithmic attenuators and amplifiers, and more particularly to programmable low noise, more accurate CMOS logarithmic attenuators/amplifiers than those disclosed in my commonly assigned U.S. Pat. No. 5,880,618.
The subject matter of this invention is similar to that of the inventor's commonly assigned U.S. Pat. No. 5,880,618, issued Mar. 9, 1999, which is incorporated herein by reference.
Logarithmic attenuator structure
10
in
FIG. 1
is essentially the same as shown in
FIG. 3
of the '618 patent. Input voltage V
IN
is applied to conductor
11
. A suitable number of transistors, in this example, Q
1
, Q
3
, Q
5
, Q
7
, and Q
9
, are connected in series between conductor
11
and conductor
12
. V
OUT
is produced on conductor
12
, and is a logarithmically attenuated representation of V
IN
. Each of series transistors Q
1
, Q
3
, Q
5
, Q
7
, and Q
9
are the same size, and each has the same on resistance. Each is biased so as to always be on. The total series resistance between V
IN
and V
OUT
is equal to the above on resistance multiplied by the number of series transistors.
Each intermediate node between the various series-connected transistors Q
1
,Q
3
. . . Q
9
of prior art
FIG. 1
is connected to a shunt transistor Q
2
, Q
4
, Q
6
, Q
8
, and Q
10
, respectively. The source electrodes of Q
2
, Q
4
, Q
6
, Q
8
, and Q
10
are connected to a fixed common mode reference voltage V
CM
on conductor
13
.
FIG. 2
shows a sequence of control voltages V
1
,V
2
. . . V
10
, the same as in
FIG. 4
of the above mentioned '618 patent. By applying the sequential control voltages V
1
, V
2
, V
3
, V
4
, V
5
as shown in the upper graph in
FIG. 2
, fairly linear attenuation measured in decibels (dB) is achieved if the on resistances of each of the shunt resistors Q
2
,Q
4
. . . Q
10
are equal.
As the number of stages each receiving a respective sequential control voltage V
1
, V
2
, V
3
etc. is increased, the number of the cusps
27
A in the gain transfer characteristic shown at the bottom of
FIG. 2
is increased, and the magnitude of each cusp is reduced. The effect of the noise signals would be significantly less if the series resistance between V
IN
and V
OUT
were significantly reduced. A problem with the logarithmic attenuator circuit shown in prior art
FIG. 1
is that “noise” signals are generated when the shunt transistors Q
2
,Q
4
. . . Q
10
are turned off.
Thus, there are unmet needs for a low noise logarithmically controlled attenuator, a low noise, low distortion logarithmically controlled amplifier, a programmable low noise, programmable logarithmically controlled amplifier, and a programmable low noise, low distortion logarithmically controlled attenuator, all of which are unmet by the prior art.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the invention to provide a CMOS logarithmic attenuator/amplifier that has lower noise than the closest prior art.
It is another object of the invention to provide a CMOS logarithmic attenuator/amplifier that has lower noise and lower distortion than the closest prior art.
It is another object of the invention to provide a programmable low noise logarithmic attenuator.
It is another object of the invention to provide a logarithmic attenuator and/or amplifier with programmable peak gain and a programmable gain range.
Briefly described, and in accordance with one embodiment thereof, the invention provides a technique for obtaining low noise, low distortion logarithmic gain/attenuation by providing a resistive attenuator (
8
A) including an input conductor (
11
) and an output conductor (
12
), a single series resistive element (QS) connected in series between the input conductor and the output conductor, and a plurality of parallel resistive elements each having a first terminal connected to the output conductor (
12
). Each of the parallel resistive elements includes an electrically controllable resistive element having a control terminal operative to control the resistance thereof and a second terminal coupled to a common conductor (
13
). A plurality of successive piecewise-linear control signals (V
1
,
2
. . . ) are applied to the control terminals of successive electrically controllable resistive elements, respectively. The plurality of successive piece-wise linear control signals are produced in response to linear changing of a gain control signal (V
GC
) from a first value to a second value.
In one embodiment, one or more additional parallel resistive elements are included in groups with each of the above parallel resistive elements, respectively. The control terminal of each parallel resistive element in each group is connected to a corresponding gain control switch that is responsive to a corresponding gain control signal. The gain/attenuation of the logarithmic attenuator is selectable by switching various combinations of the parallel resistive elements in each group into or out of parallel connection with each other. In another embodiment two or more of the logarithmic attenuators are arranged in a cascade or series connection in order to increase the linearity of the logarithmic attenuator by increasing the number of parallel resistive elements, but without excessively increasing their physical size. In another embodiment the outputs of a differential implementation of the low noise, programmable attenuator are provided as inputs to a programmable low noise differential amplifier in order to provide a programmable low noise, low distortion logarithmic differential amplifier, the outputs of which can be filtered and applied as a logarithmically amplified low noise input to an analog-to-digital converter. In another embodiment the logarithmic attenuator is included in the feedback loop of an operational amplifier.


REFERENCES:
patent: 3537014 (1970-10-01), Speth
patent: 3539831 (1970-11-01), Gilbert
patent: 3568073 (1971-03-01), McGuffin
patent: 3590366 (1971-06-01), Vaughn
patent: 3700918 (1972-10-01), Kawashima
patent: 3916193 (1975-10-01), Corte et al.
patent: 4232302 (1980-11-01), Jagatich
patent: 4475169 (1984-10-01), Gilbert
patent: 4476538 (1984-10-01), Gilbert
patent: 4500845 (1985-02-01), Ehni
patent: 4521764 (1985-06-01), Burton
patent: 5077541 (1991-12-01), Gilbert
patent: 5134722 (1992-07-01), Emslie et al.
patent: 5159280 (1992-10-01), Chadwick
patent: 5414313 (1995-05-01), Crescenzi et al.
patent: 5432478 (1995-07-01), Gilbert
patent: 5523712 (1996-06-01), Miyabe et al.
patent: 5877645 (1999-03-01), Comino et al.
patent: 5880618 (1999-03-01), Koen

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