Electrical pulse counters – pulse dividers – or shift registers: c – Applications – Measuring or testing
Reexamination Certificate
1998-06-23
2001-05-01
Wambach, Margaret R. (Department: 2816)
Electrical pulse counters, pulse dividers, or shift registers: c
Applications
Measuring or testing
C377S027000, C327S241000, C327S252000, C327S344000
Reexamination Certificate
active
06226344
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates to a method of generating a time period as defined in the precharacterizing part of claim
1
.
The invention further relates to a circuit for generating a time period.
Such a time period generation is especially suitable for use in a vertical or horizontal synchronizing circuit or in a control circuit for a switched mode power supply.
U.S. Pat. No. 5,233,232 discloses a timer circuit which provides a wide range of precise and substantially accurate time intervals. The timer circuit includes a ramp generator circuit which starts a ramp signal in response to a start signal, a comparator which compares the ramp signal with a reference voltage source for providing an end of ramp signal indicating an end of the ramp, a counter which counts a predetermined number of clock pulses starting from the end of the ramp to provide a count signal, and an AND gate which combines the end of ramp signal and the count signal to provide a signal that is delayed with respect to the start signal by a predetermined amount. U.S. Pat. No. 5,233,232 further discloses that short time intervals are generated by the ramp generator circuit only, and long time intervals are generated by performing a digital counting operation after the end of the ramp. A fixed ramp interval is generated. Consequently, the resolution of long time intervals is determined by the clock period of the clock pulses. It is further disclosed that it is possible to also adjust the ramp interval for combined ramp and counter time intervals. It is not disclosed how this should be done. It is stated that an extremely fine resolution is rarely required, or even desirable, when a long time interval is selected. Even if the ramp interval is adjusted, the resolution of the long time interval is determined by the clock period of the clock pulses, unless the clock pulse generator starts within a very accurate time with a very accurate phase after the end of the ramp. Such an accurate start stop oscillator is extremely complex.
SUMMARY OF THE INVENTION
It is an object of the invention to provide a simple method of generating a time period with a very high accuracy and with an analog resolution.
To this end, a first aspect of the invention provides a method of generating a time period as defined in claim
1
. A starting instant starts an analog integration operation to generate an integration value. At a certain instant, the analog integration operation is interrupted to start counting clock pulses. A selected number of clock pulses is counted to obtain a sub-time period. The analog integration operation is resumed at the end of the sub-time period at the integration value reached at the start of the sub-time period. The analog integration operation finishes at the instant the integration value crosses a reference value. So, three successive sub-time periods occur. A first sub-time period of integrating starts at the start instant and lasts until the counting starts, a second sub-time period during which the counter counts clock pulses, and a third sub-time period starts at the instant the counter has counted the selected number of clock pulses and lasts until the integration value has reached the reference value. The time period starts at the start of the first sub-time period and ends at the end of the third sub-time period. The accuracy of the generated time period is very high. The counting of clock pulses starts and ends at an instant related to the clock pulses. The frequency and phase of the clock pulses is completely irrelevant to the accuracy reached, as the integration operation is frozen at the very instant the counting starts and is resumed the instant the counting finishes. It is not required to start an oscillator in a very well-defined way the instant the integration operation has reached a reference level. The method according to the invention interrupts the integration operation the instant the counting starts. In practice, the accuracy is determined only by noise on the analog integration-operation step and by noise on the step of determining when the integration value crosses the reference level. These noise sources cause jitter in the duration of the generated time period. The time period is generated with a very high analog resolution by adapting the reference value or the steepness of the analog integration operation.
It is known to generate a time period or delay with either analog or digital techniques.
The accuracy of a delay generated with digital techniques is limited due to the quantized time steps of clock pulses. Impractically high clock frequencies are required if a very accurate delay is required in the order of one nano-second.
The accuracy of a delay generated with analog techniques is limited due to the signal-to-noise ratio. Analog delay may be obtained by generating an analog sawtooth by charging a capacitor with a current. The analog sawtooth is started from a starting level at the start instant. A comparator compares the sawtooth with a reference voltage. When the sawtooth crosses this reference voltage, the sawtooth is terminated. The delay runs from the start instant until the instant the sawtooth is terminated. The invention is based on the insight that there are at least three noise sources. The first noise source is charge noise in the sawtooth capacitor. When current flows for a certain time, a charge is moved. The moved charge has an error which is Poison distributed. This error is proportional to the square root of the number of moved electrons. This error is called charge noise. The charge as well as the charge noise are converted to a voltage by a capacitor. Increasing the moved charge will increase the charge noise by the square root of this moved charge. The signal-to-noise ratio, however, will increase with the square root of the moved charge. So, a large moved charge is important for a good signal to noise ratio. The ratio between the intended sawtooth and the noise can be increased by increasing the sawtooth capacitor or the reference voltage, or both. In integrated circuits, a large capacitor or a large reference voltage is unpractical. The second noise source is the voltage noise on the reference voltage. This voltage noise can be reduced by a design exhibiting a low noise density, sometimes at the expense of dissipation. The third noise source is the voltage noise of the comparator. The comparator noise can be reduced by reducing the comparator noise density and the comparator noise bandwidth. All three noise sources are added together and have a certain frequency spectrum. The comparator filters this noise spectrum with the comparator bandwidth. In order to obtain a low noise level, reduction of the comparator bandwidth to the lowest acceptable value is very important. A small bandwidth will give a longer comparator delay, but that can be compensated for. The total noise detected by the comparator is converted to timing noise by the slew rate of the sawtooth. This results in jitter on the delay. In order to obtain the lowest jitter with a given noise, the slew rate of the signal to be compared with the reference voltage should be as high as possible. For long delays it is impossible to reach a high slew rate as the maximum voltage swing of the sawtooth is limited by the maximum voltage ratings of the integrated circuit. Consequently, a long delay generated in an analog way causes substantial jitter because of the low slew rate.
The invention generates a sawtooth voltage with a high slew rate because the duration of the sawtooth is short. Consequently, the jitter is very small and the accuracy very high. The length of the delay is freely selectable with a resolution of one clock period by changing the predetermined number, and with an analog resolution by changing the reference level or a slope of the sawtooth voltage.
Advantageous embodiments are defined in the dependent claims.
An embodiment of the invention as claimed in claim
2
has the advantage that an accurate duration of the first sub period is obtained. It is guaranteed that th
Franzblau Bernard
U.S. Philips Corporation
Wambach Margaret R.
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