Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Rectangular or pulse waveform width control
Reexamination Certificate
1999-10-25
2001-09-04
Callahan, Timothy P. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Rectangular or pulse waveform width control
C327S176000, C327S122000, C327S269000, C327S291000, C375S238000
Reexamination Certificate
active
06285226
ABSTRACT:
FIELD OF THE INVENTION
The invention relates to integrated circuits (ICs). More particularly, the invention relates to a duty cycle correction circuit and method for an IC.
BACKGROUND OF THE INVENTION
Clock signals are used in virtually every IC and electronic system to control timing. For example, every time there is a rising edge on a clock signal, all the flip-flops in a circuit may change state. Frequently, both edges (rising and falling) of the clock signal are used. For example, in a Master-Slave flip-flop, data is read into the flip-flop on one edge of the clock signal, and then appears at the output terminal of the flip-flop on the other edge. Since the Master-Slave flip-flop is performing logic functions during each half of the clock cycle, the two states of the clock (high and low) are preferably each of approximately equal length. (This condition is called a “50% duty cycle”.) If one state is appreciably longer than the other, the clock signal is “unsymmetrical” (e.g., the clock signal is low longer than it is high). This limitation is not uncommon; for example, duty cycles of about 10% (i.e., 10% high, 90% low) are often seen. Under these conditions, the frequency at which a circuit can operate may be limited by the length of the shorter state (e.g., by the length of time that the clock signal is high). Therefore, the circuit operates at an unnecessarily low frequency.
To overcome this limitation, circuit designers can extract a 50% duty cycle clock from an unsymmetrical clock signal using a phase-lock loop (PLL) circuit. However, a PLL circuit consumes a great deal of silicon area. Additionally, PLLs are often analog in nature and take an extremely long time to simulate, and a design that works in one manufacturing process may stop working when manufactured using another process. Therefore, PLLs are very difficult to design, and often are not feasible in a given circuit or system. Therefore, duty cycle correction is often not possible using known circuits and methods.
Therefore, it is desirable to provide a duty cycle correction circuit and method that enables a circuit designer to correct an unsymmetrical clock to a 50% duty cycle, using a fairly simple circuit that consumes a relatively small amount of silicon area.
SUMMARY OF THE INVENTION
The invention provides a duty cycle correction circuit and method that accept an unsymmetrical input clock signal and provide therefrom an output clock signal having a 50% duty cycle. A circuit according to the invention includes an input clock terminal supplying an input clock signal, and a delay line driven by the input clock signal and supplying a plurality of intermediate clock signals delayed from the input clock signal by incremental unit delays. A clock multiplexer selects from among these intermediate clock signals, under control of a multiplexer control circuit, the clock signal that is most nearly 180 degrees offset from the input clock, i.e., the clock signal subject to a delay closest to but not exceeding half of one input clock period. The input clock signal is appropriately delayed to compensate for the delay through the clock multiplexer, then combined with the selected clock signal in an output clock generator that provides an output clock signal having a 50% duty cycle. (The term “50% duty cycle” is used herein to describe a duty cycle wherein the high pulse and the low pulse are within one unit delay of each other in length.)
The multiplexer control circuit essentially counts the number of unit delays between first (e.g., rising) edges of the input clock signal. This total number of unit delays is divided by two, thus supplying the desired number of unit delays between the first (e.g., rising) and the second (e.g., falling) edges of the output clock signal. This number is used to select the correct intermediate clock signal, i.e., the clock signal subject to a delay closest to but not exceeding half of one input clock period.
In one embodiment, the duty cycle correction circuit includes an option to disable the circuit. A disable control signal is applied to the output clock generator to select the input clock signal as the output clock signal. Therefore, no duty cycle correction is performed.
In another embodiment, the duty cycle correction circuit includes a preliminary delay stage for the delay line. The preliminary stage comprises a delay element that can selectively add either a full unit delay or a half-unit delay to the input clock signal. Using this additional delay element, the duty cycle correction circuit can supply a clock more nearly offset by 180 degrees. If the clock period spans an odd number of unit delays, the half-unit delay is inserted. If the clock period spans an even number of unit delays, a full unit delay is inserted, and the circuit operates as described above. In other embodiments, rather than adding a selectable half/full unit delay element at the beginning of the delay line, the first stage of the delay line is modified to offer a half/full unit delay option, or a full/one-and-a-half unit delay option. As long as corresponding changes are made to the select generation circuitry, as is easily done by those of ordinary skill in the art, any of these or similar changes to the delay line are easily accommodated by the circuits and methods of the invention.
In yet another embodiment, a status generator circuit is provided that provides a status signal after a predetermined number of clock cycles have elapsed. This status signal may be used by other circuits to disable the output clock signal until the output clock signal has settled into a reliably predictable pattern.
REFERENCES:
patent: 5245637 (1993-09-01), Gersbach et al.
patent: 5537069 (1996-07-01), Volk
patent: 5994938 (1999-11-01), Lesmeister
patent: 6040726 (2000-03-01), Martin
patent: 6100735 (2000-08-01), Lu
Callahan Timothy P.
Cartier Lois D.
Nguyen Minh
Xilinx , Inc.
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