Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor
Utility Patent
1997-08-12
2001-01-02
Tsai, Jey (Department: 2812)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
C438S130000, C438S131000, C438S132000, C438S467000, C438S600000, C438S601000
Utility Patent
active
06168969
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor devices and associated integrated circuit configurations and, more particularly, to bare die configurations and stacked multi-chip (bare die) assemblies with chip-integral vertical connection circuitry and a method of fabricating such die and assemblies.
2. State of the Art
As computers and other microprocessor-dependent electronics become physically more compact and operate at ever-faster speeds, the amount of “real estate” available on circuit boards and other component-supporting substrates becomes ever-smaller. Various die packaging schemes have evolved to promote greater component density, one of the most recently prevalent being surface mount technology (SMT). In an SMT package, “footprint” size is reduced by use of small leads placed at a fine pitch, sometimes in combination with staggered rows of terminal bond pads about substantially the entire exterior of a circuit package. The SMT pads or lead ends generally extend immediately below the package and not first laterally, as in most prior art dual-in-line (DIP) and small-outline J-lead packages (SOJ). Another attempt to increase component density by vertical component orientation has resulted in the so-called zig-zag inline package (ZIP).
Multi-chip modules (MCM's), wherein several chips or dice for the same or different functions are mounted in a common package, generally mount all dice in the module on a supporting substrate in the same horizontal plane, such as is the case in a single in-line memory module (SIMM) including a plurality of dynamic random access memory (DRAM) dice.
It has, however, been recognized that it may be desirable in certain applications to enhance component density by laterally stacking vertically-oriented die or die support substrates on a transversely-oriented carrier substrate to which electrical access is secured via edge connect structures on the die or die support substrates. U.S. Pat. Nos. 5,266,833; 4,983,533; and 4,764,846 are exemplary of state of the art lateral die stacking approaches. Such structures, while increasing component density, obviously require conductors extending to at least one side of the stacked die or die support substrate, which may effectively limit the number of connections to the carrier substrate. If terminals are placed on more than one edge of a die (see the '833 patent), the die support substrate or other bus structure becomes somewhat complex. Further, edge-accessing die or die support substrates dictates that all inter-die or inter-die support electrical connections must be effected through the carrier substrate without the potential for direct die-to-die connection.
It has also, however, been recognized that it may be desirable in certain applications to vertically stack horizontally-disposed dice in two or more layers. U.S. Pat. Nos. 5,481,134; 5,481,133; 5,468,997; 5,455,445; 5,434,745; and 5,128,831 are exemplary of state of the art vertical die stacking approaches. Also illustrative of the state of the art in that regard is “Laminated Memory: A new 3-Dimensional Packaging Technology for MCM's”,
Proceedings of
1994
IEEE Multi
-
Chip Module Conference,
pp. 58-63. Further examples of such structures are the commercially available Micro SMT Packages from Micro SMT, Inc., depicted and described in a Micro SMT, Inc. brochure bearing a 1993 copyright. Existing vertical stack MCM's, while increasing component density, usually laterally offset active and passive devices in a given plane or layer of a stack from the vertical, interlayer conductors, necessitating the use of horizontal circuit traces extending from the devices to the edge of each die or at the very least to a peripheral area of the die. Such offsets increase the lateral size or footprint of the stack and are somewhat limiting with respect to the number of devices per layer, even if the vertical conductors are formed as contact holes or vias in the silicon die material itself, which is not common practice. It has also been suggested in the art to employ diffused metal pillars connected to horizontally offset active devices of the die by laterally extending circuit traces.
Therefore, it would be extremely advantageous to form passive and active devices and vertical conductors, hereinafter generally referred to herein as vias, respectively on and within dice, and in vertically superimposed relationship to the extent possible. Such an approach would permit electrical connection of a die to other dice or a supporting substrate such as a printed circuit board (PCB) through the back side of the die, using that heretofore unused or underemployed die side in lieu of the so-called “active” or top side. It would also be highly beneficial to minimize the number of vias when stacking dice by accessing a single, commonly-required via within the die perimeter for (by way of example for a DRAM die) CAS, RAS, I/O, power, and ground from each level or plane in the die stack, thus requiring dedicated vias to each level only for the chip-select function. Finally, it would simplify and expedite fabrication of such die structures to employ via formation techniques which do not involve forming and filling holes extending vertically through the die.
SUMMARY OF THE INVENTION
The present invention comprises a method for forming a bare die suitable for back side electrical connection to a carrier, as well as for multi-layer, or vertically stacked, multi-chip (bare die) assemblies employing metalzed silicon vias for vertical interconnection of the dice to each other and to a carrier substrate to which the die stack is electrically connected. The present invention provides the ability to fabricate a protected package of stacked dice with a surface-mount terminal array on the bottom or back side of the lowermost die for mounting to a conductor-bearing carrier substrate.
The present invention includes at least one, and preferably a plurality, of silicon or other suitable die (such as gallium arsenide) on which integrated electronic devices are formed and through which vertically-extending electrical conductors (vias) extend in a pattern to maximize component and circuit density on the die.
In the method of the invention, vias are formed as conductive pillars through the die material from the top or active surface thereof to the bottom. The pillars may be formed by doping of a conductive material onto the top die surface and gravity diffusion of the conductor through the silicon. Vertical diffusion may be enhanced, and lateral diffusion curtailed, by electrochemically anodizing the die using a mask to create the desired via pattern, or by appropriate crystallographic orientation of the silicon die material to facilitate channeling of the conductive material through the silicon matrix. Alternatively, ion implantation of the conductor through a suitably patterned mask may be employed to create the vias.
Subsequent to via formation, active or passive integrated devices or components and other structures may be formed on the active surface of the die. If an active component, the structure is formed by one of several epitaxial film deposition and doping processes as known in the art. If a passive component or bond pad, the structure may likewise be formed by any additive or subtractive material deposition process, or combination thereof, as known in the art. The components and surface conductors, such as bond pads, are preferably formed in superimposition to the vias rather than laterally offset therefrom.
If the die in question is employed singly on a supporting substrate, or is the uppermost die of a stack, an insulating, protective layer such as silicon dioxide, doped silicon dioxide (PSG, BPSG), silicon nitride or a polyimide may be applied over the entire active surface since all electrical connections are made from the back of the die. If a die stack is formed, a protective layer as required may additionally be formed about the sides of the stack or a shielding adhesive applied between the stacked dice
Britt Trask
Jones Josetta
Micro)n Technology, Inc.
Tsai Jey
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