Static information storage and retrieval – Addressing – Including particular address buffer or latch circuit...
Reexamination Certificate
2000-08-31
2001-08-07
Hoang, Huan (Department: 2818)
Static information storage and retrieval
Addressing
Including particular address buffer or latch circuit...
C365S233100, C365S189020
Reexamination Certificate
active
06272064
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The present invention relates generally to static memory devices and in particular the present invention relates to a memory device which combines multiple data communication operations in a common integrated circuit.
BACKGROUND OF THE INVENTION
Modern memory devices are available in numerous configurations with different operating specifications. For example, dynamic, static and non-volatile memories are available in multiple architectures and can be operated in different modes. Those skilled in the art will recognize page mode, synchronous, burst, pipe line, and bus efficient (BE) as examples of different data communication operations commercially available.
One type of memory is the static random access memory (SRAM). An SRAM is designed to store data in memory cells formed as a static latch circuit. This type of memory does not require the data refresh operations necessary in a conventional DRAM. The SRAM, however, requires additional integrated die area to fabricate a memory cell.
With the constant development of faster computer and communication applications, the data rates in which a memory circuit must operate continue to increase. To address the need for increased data rates, a variety of memories are produced in a variety of designs which provide different methods of reading from and writing to the memory cells of the memory. Page mode operations are defined by the method of accessing a row of a memory cell array and randomly accessing different columns of the array. Data stored at the row and column intersection can be read and output while that column is accessed. Page mode memories require access steps which limit the communication speed of the memory circuit.
Another type of memory is a burst access memory which receives one address of a memory array on external address lines and automatically addresses a sequence of columns without the need for additional column addresses to be provided on the external address lines. By reducing the external address input signals, burst memory circuits are capable of outputting data at significantly faster communication rates than the above described memory circuits.
Synchronous memory devices, either dynamic or static, operate in synchronization with an externally provided clock signal and can typically function in burst read and write modes to reduce external address input signals. Synchronous burst SRAM devices, known as PB
1
and PB
2
, are also available as pipelined and non-pipelined (flow-through) devices. Inactive data bus times are often experienced when changing the operation of an SRAM from a write operation to a read operation. This “idle” bus time is eliminated in bus efficient (BE) memory devices. These memories receive external addresses one or more clock cycles prior to its corresponding data.
The above described synchronous and BE memories are manufactured and sold as separate devices which require specifically designed integrated circuits. For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a single integrated circuit memory device which can be operated in either synchronous or bus efficient (BE) modes.
SUMMARY OF THE INVENTION
The above mentioned problems with integrated circuit memory devices and other problems are addressed by the present invention and which will be understood by reading and studying the following specification. A memory device is described which is operable in both a synchronous mode and a bus efficient mode.
In particular, the present invention describes an integrated memory circuit comprising address register circuitry having first and second address propagation paths, input data register circuitry having first and second data propagation paths, and control circuitry coupled to the address register circuitry and the input data register circuitry to control the address and input data propagation paths. The integrated memory circuit can operate in either a synchronous mode, or a bus efficient mode.
In another embodiment a static random access memory (SRAM) is provided that is operable in both a synchronous mode and a bus efficient mode. The SRAM comprises an array of static memory cells, an address input connection coupled to an external address bus, a data input connection coupled to an external data bus, and an address register circuit having an input coupled to the address input connection. The address register circuit comprises first and second address propagation paths from the address input connection to an output of the address register circuit. The first address propagation path is adapted to couple an address from the address input connection to the output of the address register circuit within one system clock cycle. The second address propagation path is adapted to couple an address from the address input connection to the output of the address register circuit in more than one system clock cycle. A data register circuit is provided and coupled to the data input connection. The data register circuit comprises first and second data propagation paths from the data input connection to an output of the data register circuit. The first data propagation path is adapted to couple data provided on the data input connection to the output of the data register circuit within one system clock cycle. The second data propagation path is adapted to couple data provided on the data input connection to the output of the data register circuit in more than one system clock cycle. The SRAM further includes control circuitry coupled to the address register circuit and the data register circuit for controlling address and data propagation path selection.
A static random access memory (SRAM) is provided that comprises address register circuitry having a plurality of address propagation paths, input data register circuitry having a plurality of data propagation paths, and control circuitry coupled to the address register circuitry and the input data register circuitry to control the address and input data propagation paths. The SRAM can be operated in either a mode where data provided on an external data line is synchronized with a corresponding memory address, or a mode where data provided on an external data line lags a corresponding memory address.
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Gans Dean
Wilford John R.
Auduong Gene N.
Hoang Huan
Micro)n Technology, Inc.
Schwegman Lundberg Woessner & Kluth P.A.
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