Chip size semiconductor package and fabrication method thereof

Details Chip size semiconductor package and fabrication method thereof Chip size semiconductor package and fabrication method thereof

1998-06-09

2001-05-01

Cuchlinski, Jr., William A. (Department: 3661)

Electricity: conductors and insulators

Boxes and housings

Hermetic sealed envelope type

C361S767000, C257S686000, C257S692000, C257S693000, C257S690000, C257S773000, C257S777000, C438S109000

Reexamination Certificate

active

06225558

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor package and a fabrication method thereof, and in particular to a chip size semiconductor package (CSP) and a fabrication method thereof.
2. Background of the Related Art
FIG. 1
illustrates a conventional thin small on-line package (TSOP). The problems encountered in the conventional thin small on-line package are described in the U.S. Pat. No. 5,363,279 ('279).
FIG. 2
illustrates a bottom lead package (BLP) of the '279 patent, which is assigned to the same assignee as the present invention. The BLP has a disadvantage in that the reliability of the solder joint is decreased compared to the TSOP. In the conventional BLP, if there is not a solder joint between a lead and a printed circuit board (PCB), a delamination and a cracking problem occur in the solder joint. In addition, since the conventional TSOP and BLP shown in
FIGS. 1 and 2
are fully sealed by a molding compound, it is difficult to effectively radiate the heat generated in the semiconductor chip.
The above references are incorporated by reference herein where appropriate for appropriate teachings of additional or alternative details, features and/or technical background.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a chip size semiconductor package and a fabrication method thereof that substantially overcome one or more of the problems encountered in the background art.
Another object of the present invention is to provide a chip size semiconductor package and a fabrication method thereof that enhances solder joint reliability to a lead frame.
Another object of the present invention is to provide a chip size semiconductor package and a fabrication method thereof that enhances a mounting capability when mounting a semiconductor package on a printed circuit board (PCB).
Another object of the present invention is to provide a chip semiconductor package and a fabrication method thereof that effectively radiates the heat generated in a semiconductor chip.
Another object of the present invention is to provide a chip size semiconductor package and a fabrication method thereof that provides a light and compact CSP.
To achieve at least the above objects in a whole or in parts, there is provided a chip size semiconductor package according to the present invention that includes a semiconductor chip having a plurality of bonding pads, a plurality of first leads extended from both sides of an upper surface of the semiconductor chip for corresponding with the bonding pads, a plurality of conductive members for electrically coupling the bonding pads and the first leads, a plurality of second leads formed on upper surfaces of the first leads, wherein the second leads have first portions formed on upper outer portions of the first leads and second portions extended from the first portions and upwardly bent, and a molding portion for molding the conductive members formed on the semiconductor chip, the first leads and the first portions of the second leads in a manner that the second portions of the second leads are exposed.
To further achieve the above objects, there is provided a chip size semiconductor package fabrication method according to the present invention that includes the steps of preparing a semiconductor chip having a plurality of bonding pads, forming a plurality of first leads on both sides of the semiconductor chip for corresponding with the bonding pads, forming a plurality of second leads having first portions and second portions on the upper outer end portions of the first leads wherein the first portions are bonded to the first leads and the second portions protrude from the semiconductor chip, electrically coupling the bonding pads and the first leads using connection members, forming a molding portion for sealing the connection members formed on the semiconductor chip, the first leads and the first portions of the second leads so that the second portions of the second leads are exposed, and forming the second portions of the second leads.
Additional advantages, objects, and features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention. The objects and advantages of the invention may be realized and attained as particularly pointed out in the appended claims.


REFERENCES:
patent: 4890154 (1989-12-01), Sahakian
patent: 5053852 (1991-10-01), Biswas et al.
patent: 5363279 (1994-11-01), Cha
patent: 5583375 (1996-12-01), Tsubosaki et al.
patent: 5835988 (1998-11-01), Ishii
patent: 6002167 (1999-12-01), Hatano et al.
patent: 6018191 (2000-01-01), Murakami et al.

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