Static information storage and retrieval – Addressing – Plural blocks or banks
Reexamination Certificate
1999-12-21
2001-04-10
Elms, Richard (Department: 2824)
Static information storage and retrieval
Addressing
Plural blocks or banks
C365S189040, C365S189080, C365S230090
Reexamination Certificate
active
06215719
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a memory device, in particular, to a DRAM (dynamic random access memory) used as a main memory in a computer or the like.
This application is based on Patent Application No. Hei 10-365556 filed in Japan, the contents of which are incorporated herein by reference.
2. Description of the Related Art
In consideration of the manufacturing costs and so on, DRAMs are generally used as the main memory of a computer or the like. In the operation of continuously reading or writing internal data of the DRAM, a command used for such a continuous operation is set in advance in the DRAM, a line address is selected, and then column addresses are selected. In order to continuously read or write the data of the next line, a similar operation is necessary, that is, the address signal of the next line must be selected, and then the addresses of the relevant columns must be selected.
In addition, a dedicated memory device in which the above-explained continuous reading/writing operation is possible is known; however, in such a device, the speed of reading or writing data is important and thus the random access function is impossible. That is, in the conventional memory device, the random access function and the continuous reading/writing function (of the line and column addresses) are incompatible.
As described above, in the operation of continuously reading or writing internal data in the DRAM, a command assigned to such a continuous operation is set in advance in the DRAM, a line address is selected, and then column addresses are selected, thereby starting the continuous reading or writing operation.
If it is assumed that line address A is selected, after the data of the last column in the designated line of address A is read or written, the data of the first column of the next line of address A+1 is continuously read or written. At this line shift, it is also necessary to select the next-line address A+1 and the relevant column address, that is, the time for selecting the above line address A+1 and the column address is necessary, so that it is very difficult to further improve the data reading/writing speed.
SUMMARY OF THE INVENTION
In consideration of the above circumstances, an objective of the present invention is to provide a memory device in which when the data of the next address is continuously read or written, the operation of selecting the next line and relevant column addresses is unnecessary, thereby improving the data-writing/reading speed in comparison with a conventional DRAM.
Therefore, the present invention provides a memory device comprising:
a memory cell comprising at least two banks; and
a line-address counting section for making a designated line of one of the banks active, wherein before a reading or writing operation of data of the designated line is finished, the line-address counting section makes the next designated line of another bank active.
In the above structure, the line-address counting section may consist of line address counters provided corresponding to each bank.
The above memory device may further comprise column address counters, provided corresponding to each bank, for making columns of the relevant bank active.
Additionally, the memory device may further comprise a bank selecting switch for selecting one of the banks, wherein when the counting operation of the column address counter provided for a bank is finished, the bank selecting switch switches the current bank and selects another bank, and another column address counter provided for the selected bank starts counting.
According to the present invention, it is possible to omit the time necessary for selecting the following line and relevant column addresses, and thus the data reading/writing speed can be improved.
REFERENCES:
patent: 5274596 (1993-12-01), Watanabe
patent: 5506810 (1996-04-01), Rumas
patent: 5598372 (1997-01-01), Matsumoto et al.
patent: 5691955 (1997-11-01), Yamauchi
patent: 58-115684 (1983-07-01), None
patent: 60-253087 (1985-12-01), None
patent: 3-61276 (1991-09-01), None
patent: 4-311896 (1992-11-01), None
patent: 6-131248 (1994-05-01), None
Elms Richard
Foley & Lardner
NEC Corporation
Nguyen Hien
LandOfFree
Memory device having line address counter for making next... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Memory device having line address counter for making next..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Memory device having line address counter for making next... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2537322