Semiconductor article with porous structure

Details Semiconductor article with porous structure Semiconductor article with porous structure

1998-12-16

2001-06-12

Saadat, Mahshid (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Bulk effect device

Bulk effect switching in amorphous material

C257S347000, C438S478000

Reexamination Certificate

active

06246068

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a semiconductor substrate and a producing method thereof. More specifically, the present invention relates to dielectric isolation or a producing method of a single-crystal semiconductor on an insulator and a single-crystal compound semiconductor on a Si substrate, and further relates to a method of producing a semiconductor substrate suitable for an electronic device or an integrated circuit formed at a single-crystal semiconductor layer.
RELATED BACKGROUND ART
Formation of a single-crystal Si semiconductor layer on an insulator is widely known as a silicon on insulator SOI. This technique has been extensively researched since a device utilizing the SOI technique has a number of advantages which cannot be achieved by a bulk Si substrate forming the normal Si integrated circuit. Specifically, for example, the following advantages can be achieved by employing the SOI technique:
1. Dielectric isolation is easy and high integration is possible;
2. Radiation resistance is excellent;
3. Floating capacitance is reduced and high speed is possible;
4. Well process can be prevented;
5. Latch-up can be prevented; and
6. Fully depleted (FD) field effect transistor is achieved through film thickness reduction.
These are described in detail, for example, in the literature of Special Issue: “Single-crystal silicon on non-single-crystal insulators”; edited by G. W. Cullen, Journal of Crystal Growth, volume 63, no. 3, pp. 429-590 (1983).
Further, over the past few years, the SOI has been largely reported as a substrate which realizes the acceleration of a MOSFET and low power consumption (IEEE SOI conference 1994). Since an element has an insulating layer at its lower part when employing the SOI structure, an element separation process can be simplified as compared with forming an element on a bulk silicon wafer so that preparing a device can take less time. Specifically, in addition to achieving the higher performance, reduction of the wafer cost and the process cost is expected as compared with a MOSFET or IC on bulk silicon.
Particularly, the fully depleted (FD) MOSFET is expected to achieve higher speed and lower power consumption through improvement in driving force. In general, a threshold voltage (Vth) of a MOSFET is determined by the impurity concentration at a channel portion. On the other hand, in case of the FD MOSFET using the SOI, a depletion layer is also subjected to an influence of a film thickness of the SOI. Thus, for producing the large scale integrated circuits at high yield, uniformity of the SOI thicknesses has been strongly demanded.
On the other hand, a device on a compound semiconductor has high performance, such as, high speed and luminescence, which cannot be achieved by Si. Presently, such a device is normally formed in an epitaxial layer grown on a compound semiconductor substrate, such as a GaAs substrate.
However, there is a problem that the compound semiconductor substrate is expensive while low in mechanical strength, so that a large area wafer is difficult to produce.
Under these circumstances, an attempt has been made to achieve the heteroepitaxial growth of a compound semiconductor on a Si wafer which is inexpensive and high in mechanical strength so that a large area wafer can be produced.
Referring back to the SOI, research on the formation of the SOI substrates has been active since the 1970s. In the beginning, the research was performed in connection with the SOS (sapphire on silicon) method, which achieves the heteroepitaxial growth of single-crystal silicon on a sapphire substrate being an insulator, the FIPOS (fully isolated by porous oxidized silicon) method, which forms the SOI structure by dielectric isolation based on oxidation of porous Si, and the oxygen ion implantation method.
In the FIPOS method, an n-type Si layer is formed on a surface of a p-type Si single-crystal substrate in an island shape through the proton ion implantation (Imai and collaborator, J. Crystal Growth, vol. 63, 547 (1983)) or through the epitaxial growth and the patterning, then only the p-type Si substrate is rendered porous so as to surround the Si island from the surface by means of the anodizing method in a HF solution, and thereafter the n-type Si island is dielectric-isolated through accelerating oxidation. In this method, there is a problem that the isolated Si region is determined in advance of the prepared device so that the degree of freedom of device designing is limited.
The oxygen ion implantation method is a method called SIMOX first reported by K. Izumi. After implanting about 10
17
to 10
18
/cm
2
of oxygen ions into a Si wafer, the ion-implanted Si wafer is annealed at the high temperature of about 1,320° C. in the atmosphere of argon/oxygen. As a result, oxygen ions implanted with respect to a depth corresponding to a projection range (Rp) of ion implantation are bonded with silicon so as to form a silicon oxide layer. On this occasion, a silicon layer which has been rendered amorphous at an upper portion of the silicon oxide layer due to the oxygen ion implantation is also recrystallized so as to be a single-crystal silicon layer. Conventionally, there have been a lot of defects included in the silicon layer on the surface, that is, about 10
5
/cm
2
. On the other hand, by setting an implantation amount of oxygen to about 4×10
17
/cm
2
, defects are successfully reduced to about 10
2
/cm
2
. However, since the ranges of implantation energy and implantation amount for maintaining the quality of the silicon oxide layer, the crystalline property of the surface silicon layer and the like are so narrow that thicknesses of the surface silicon layer and the buried silicon oxide (BOX: buried oxide) layer were limited to particular values. For achieving a desired thickness of the surface silicon layer, it was necessary to perform sacrificial oxidation and epitaxial growth. In this case, there is a problem that, since the degradation caused through these processes is superimposed on the distribution of thicknesses, the thickness uniformity deteriorates.
It has been reported that a formation failure region of silicon oxide called a pipe exists in the BOX layer. As one cause of this, the forcing matter upon implantation, such as dust, is considered. In the portion where the pipe exists, the deterioration of the device characteristic results from leaks between an active layer and a support substrate.
Further, since the amount of ion implantation in the SIMOX is large as compared with the ion implantation in the ordinary semiconductor process, implantation time is lengthy even after developing the apparatus to be used exclusively for that process. The ion implantation is performed by raster-scanning an ion beam of a given current amount or expanding the beam so that an increment of the implantation time is predicted following an increment in the area of the wafer. Further, in the high temperature heat treatment of the large-area wafer, it has been pointed out that a problem of occurrence of slip due to the temperature distribution in the wafer becomes more severe. In SIMOX, the heat treatment is essential at high temperature, that is, 1,320° C., which is not normally used in silicon semiconductor processes, so that there has been concern that this problem, including the development of the apparatus, becomes more significant. On the other hand, apart from the foregoing conventional SOI forming method, attention has been recently given to the method which forms the SOI structure by sticking a Si single-crystal substrate to a thermal-oxidized Si single-crystal substrate through heat treatment or using adhesives. In this method, it is necessary to form an active layer for the device into a uniform film. Specifically, it is necessary to form a Si single-crystal substrate of a thickness of as much as hundreds of microns into a film of several microns or less. There are three kinds of methods for thickness reduction as follows:
1. Thickness reduction through polishing;
2. Thickness reduction through local plas

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