Static information storage and retrieval – Floating gate – Multiple values
Reexamination Certificate
1997-12-12
2001-08-21
Le, Vu A. (Department: 2818)
Static information storage and retrieval
Floating gate
Multiple values
C365S185200, C365S185210
Reexamination Certificate
active
06278632
ABSTRACT:
TECHNICAL FIELD
The present invention relates to non-volatile memory systems, and more specifically, to a method for determining whether a multistate memory cell contained in such a system has been properly programmed by detecting an over-programmed or under-programmed condition.
BACKGROUND OF THE INVENTION
In conventional single-bit per cell memory devices, the memory cell assumes one of two information storage states, either an “on” state or an “off” state. The binary condition of “on” or “off” defines one bit of information. As a result, a memory device capable of storing n-bits of data requires (n) separate memory cells.
Increasing the number of bits which can be stored using single-bit per cell memory devices depends upon increasing the number of memory cells on a one-for-one basis with the number of bits of data to be stored. Methods for increasing the number of memory bits stored in a memory device composed of single-bit capacity cells have relied upon manufacturing larger die which contain more memory cells or using improved photolithography techniques to build smaller memory cells. Reducing the size of a memory cell allows more cells to be placed on a given area of a single die.
An alternative to single-bit per cell designs is the storage of multiple-bits of data in a single memory cell. One type of memory in which this approach has been followed is an electrically erasable and programmable device known as a flash memory cell. In flash cells, programming is carried out by applying appropriate voltages to the source, drain, and control gate of the device for an appropriate time period. This causes electrons to tunnel or be injected from a channel region to a floating gate. The amount of charge residing on the floating gate determines the voltage required on the control gate to cause the device to conduct current between the source and drain regions. This voltage is termed the threshold voltage, V
t
, of the cell. Conduction represents an “on” or erased state of the device and corresponds to a logic value of one. An “off” or programmed state is one in which current is not conducted between the source and drain regions and corresponds to a logic value of zero. By setting the threshold voltage of the cell to an appropriate value, the cell can be made to either conduct or not conduct current for a given set of applied voltages. Thus, by determining whether a cell conducts current at the given set of applied voltages, the state of the cell (programmed or erased) can be found.
A multi-bit or multistate flash memory cell is produced by creating multiple, distinct threshold voltage levels within the device. Each distinct threshold voltage level corresponds to a value of a set of data bits, with the number of bits representing the amount of data which can be stored in the multistate cell. This method allows multiple bits of binary data to be stored within the same memory cell. When reading the state of the memory cell, the threshold voltage value or range of values for which the memory cell conducts current (as determined by comparison with a sense amplifier having a preselected reference value) corresponds to a binary decoded value representing the programmed data. The threshold voltage level for which the cell conducts thus corresponds to a bit set representing the data programmed into the cell. Proper data storage requires that the multiple threshold voltage levels of a multistate memory cell be separated from each other by a sufficient amount so that a level of a cell can be programmed or erased in an unambiguous manner. As noted, the specific relationship between the data programmed into the memory cell and the threshold voltage levels of the cell depends upon the data encoding scheme adopted for the cells.
In programming a multistate memory cell, the objective is to apply a programming voltage over a proper time period to store enough charge in the floating gate to move the cell's threshold voltage to a desired level. This level represents a state of the cell corresponding to an encoding of the data which is to be programmed into the cell.
However, division of the threshold voltage range for a two state (one bit) cell into multiple threshold voltage levels reduces the margin (threshold voltage difference) between levels. This necessitates tighter system design tolerances and reduced programming verification noise margins so that adjacent levels can be differentiated and programming errors (over-programming or under-programming of a cell) reduced.
It is necessary to be able to program multiple bits (and as a result, multiple memory cells) at the same time in order to produce a commercially desirable memory system which can be programmed within a reasonable amount of time. However, a problem arises when a number of bits are to be programmed at the same time. This is because the characteristics of each bit are different (due to minor variations in the structure and operation of the semiconductor devices which comprise the memory cells), so that variations in the programming speed of different cells will typically occur. This results in bits that become programmed faster than others, and the possibility that some bits will be programmed to a different state (the cell will be programmed to a different threshold voltage level) than intended.
As noted, fast programming of multiple memory cells can result. in undershooting or overshooting the desired threshold voltage level of some cells, producing an error in the data being stored. In some flash memory systems, this problem. can remain unknown and result in a long (and unproductive) programming cycle. In the case of overshooting the threshold voltage range, at standard memory system would continue programming the cells, which would serve to increase the over-shoot. This car. occur because the memory system is controlled to carry out the programming operation until the programming data compares with the data applied or a maximum pulse number, voltage, and programming time occur before it aborts and sets an error flag (or performs the programming operation at an alternate storage location). In mass storage systems where programming speed is a key performance criteria and lengthy re-programming and erase operations are not desirable, a method for detecting and handling improper programming (under or over-programming) of bits during programming operations would be more efficient.
What is desired is a method of detecting an under-programming or over-programming condition in a multistate memory cell in order to properly and efficiently program the cell.
SUMMARY OF THE INVENTION
The present invention is directed to a method for detecting an under-programming or over-programming condition in a multistate memory cell. The method uses three sense amplifiers, each with an associated reference cell which produces a reference voltage for input to each of the sense amplifiers. Control circuitry is used which allows the reference cell currents to be varied to produce the reference voltages or pairs of reference voltages needed to accurately determine the threshold voltage and hence state of a programmed or erased memory cell. This information is used by a controller to determine if a memory cell has been over-programmed, under-programmed, or properly programmed. If the cell has not been properly programmed, then additional programming pulses are applied (in the case of under-programming) or an error flag is set and the programming algorithm is terminated (in the case of an over-programmed cell).
Further objects and advantages of the present invention will become apparent from the following detailed description and accompanying drawings.
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patent: 53863
Le Vu A.
Micro)n Technology, Inc.
Schwegman Lundberg Woessner & Kluth P.A.
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