Dual UART device with a reduced package pin number

Pulse or digital communications – Transceivers – Transmission interface between two stations or terminals

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Details

375239, H04B 138, H04L 516

Patent

active

058258159

ABSTRACT:
A circuit arrangement between an input/output (I/O) integrated circuit (IC) and an I/O coupler IC includes a first universal asynchronous receiver-transmitter (UART) and a second UART provided within the I/O IC, each of the UART having a plurality of output serial terminals and input serial terminals, a first pulse position modulation (PPM) circuit connected to the parallel output terminals of the first UART and the second UART and having an output pin, a first pulse position demodulation (PPDM) circuit connected to the parallel input terminals of the first UART and the second UART and having two input pins, a second PPDM circuit provided within the I/O coupler IC and connected to the output pin of the first PPM circuit with two sets of output terminals, a second PPM circuit provided within the I/O coupler IC and connected to the input pins of the first PPDM circuit with two sets of input terminals, two voltage converters each respectively connected with a set of input terminals of the second PPM circuit and a set of output terminals of the second PPDM circuit and having a set of input parallel pins and a set of output parallel pins, a control circuit/clock generator provided within the I/O IC and having two output pins, and a control circuit provided within the I/O coupler IC and having two input pins connected to the output pins of the control circuit/clock generator.

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patent: 5703871 (1997-12-01), Pope et al.

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