Method for forming dielectric within a recess

Details Method for forming dielectric within a recess Method for forming dielectric within a recess

1999-11-02

2001-07-24

Bowers, Charles (Department: 2813)

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

C438S424000, C438S435000, C438S436000

Reexamination Certificate

active

06265281

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to the field of semiconductor assembly, and more particularly to a method for forming a dielectric layer such as a trench isolation layer.
BACKGROUND OF THE INVENTION
A common structure formed during the manufacture of a semiconductor device such as memory, logic, microprocessors, etc., includes a shallow trench isolation structure. This structure can be formed by depositing a dielectric layer
10
such as a tetraethyl orthosilicate glass (TEOS) or borophosphosilicate glass (BPSG) based oxide or other dielectric in a narrow trench
12
in a substrate assembly
14
such as a monocrystalline silicon wafer as shown in
FIG. 1. A
typical use of this structure is to electrically isolate two adjacent active areas
16
. During formation of the structure, for example using chemical vapor deposition (CVD), undesirable impurities such as carbon or unoxidized silicon can be introduced into the dielectric layer. To render the impurities functionally inert, a heating step such as an anneal can be performed to oxidize the impurities and also to anneal the oxide.
As shown in
FIG. 2
, annealing the dielectric causes it to expand from the addition of molecular oxygen. The original volume of the dielectric layer from
FIG. 1
is depicted schematically in
FIG. 2
as
20
, while the volume after expansion is depicted as
22
. Expansion will generally include a volume increase of from about 0.5% to about 5.0%, depending on the dielectric and the amount and composition of undesirable impurities in the dielectric. As the dielectric is annealed the expanding volume of the dielectric layer creates stress gradients
24
at the trench
12
in the substrate assembly
14
under the expanding the dielectric layer and also stresses the dielectric itself, for example along the midline of the trench, which results in difficulties during subsequent processing. For example, the dielectric under stress etches at a different rate than the nonstressed dielectric, as does the stressed substrate assembly when compared to the etch rate of the nonstressed substrate assembly.
A process which has been used to overcome this problem includes forming the dielectric such that it has a variation in its original thickness so that regions under stress are thinner than the nonstressed regions which will etch more quickly. Other processes which have been used to overcome this problem include flowing the dielectric, which requires an undesirably high temperature, and providing special cap layers that protect the dielectric during etching. These can be complicated, inconsistent processes which produce variable results.
A method for forming a dielectric layer which reduces or eliminates the problems described above would be desirable.
SUMMARY OF THE INVENTION
The present invention provides a new method which reduces problems associated with the manufacture of semiconductor devices, particularly problems resulting from stresses placed on dielectrics and substrate assemblies from expansion of a dielectric layer during annealing. In accordance with one embodiment of the invention used during the formation of a semiconductor device a semiconductor substrate assembly such as a semiconductor wafer having at least one recess therein is provided. A first dielectric layer is formed in the recess and is then heated, such as by annealing. Next, a second dielectric layer is formed directly on the first dielectric layer within the recess and the first and second layers are then heated or annealed.
By forming the dielectric layer in two separate steps, the first layer can be formed thin enough so that it does not impinge on itself and has adequate space to expand without stressing the substrate assembly or itself. The second dielectric layer is formed so that it does impinge on itself and is then annealed, but the volume increase and stress placed on the substrate assembly and the first and second dielectric layers are greatly reduced over prior processes.


REFERENCES:
patent: H204 (1987-02-01), Oh et al.
patent: 4666566 (1987-05-01), Fulton et al.
patent: 4952524 (1990-08-01), Lee et al.
patent: 5346584 (1994-09-01), Nasr et al.
patent: 5786263 (1998-07-01), Perera
patent: 5858858 (1999-02-01), Park et al.
patent: 5055360 (1993-03-01), None
“Silicon Processing for the VLSI Era”, vol. 2: Process Integration, by Stanley Wolf, PhD, Lattice Press, p. 68, copyright 1990.

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