Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
1999-10-25
2001-01-16
Mai, Son (Department: 2818)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185170
Reexamination Certificate
active
06175523
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to the field of flash memory devices. More particularly, the invention relates to both a mechanism and method for precharging NAND-based flash memory devices.
BACKGROUND OF THE INVENTION
The overall array architecture for memory section of a typical NAND-based flash memory device comprises a core memory accessed by an upper and lower bank of page buffers and a right and left bank of word line decoders. The core memory contains information stored in blocks of memory and individual memory cells within the blocks. The right and left word line decoders are used to access specific memory cells within each memory block and the upper and lower bank of page buffers provide the input and output circuitry for each memory cell.
The architecture of one core cell block in the typical NAND-based flash memory device comprises the individual memory elements and select gates. The memory elements and select gates are embodied in non-volatile, floating gate transistors that may be programmed to a logic state of 0, 1, or other states depending on the particular type of transistor and programming used. The control gates of the transistors that comprise the individual memory elements and select gates in each core cell block are addressed by word lines controlled by the addressing system. The memory elements are connected in series with each other and the select gates. The select gates, at the ends of the chain of memory cells, are connected with either the array common voltage Vss or a bitline. A page buffer is connected with a core cell block via a bitline. The page buffer includes transistors and supporting circuitry that regulate the flow of data into and out of the core cell block and into and out of the external system.
One problem of the above architecture is that the bitline inherently has a large capacitance and thus has a relatively slow speed of response when data is extracted, i.e. read, from memory elements due to the necessary charging and discharging time of the bitline connected with each cell. Typically, the time it takes to charge the bitline to the voltage level necessary for sensing is larger than the time it takes to discharge the bitline. Thus, to decrease the cycle time for reading a specific word line, it is more advantageous to produce a mechanism or method to decrease the charging time rather than the discharging time of each bitline to be read.
BRIEF SUMMARY OF THE INVENTION
In view of the above, a precharging mechanism and method of precharging a flash memory device is provided.
A first aspect of the present invention is directed towards a method for precharging a flash memory device. The flash memory device comprises a plurality of core cell blocks containing flash memory cells, a plurality of page buffers and a plurality of bitlines. Each of the page buffers is in communication with all of the core cell blocks via a unique bitline. The method includes charging at least one of the bitlines to a preset voltage during a portion of a precharge cycle. The logic state of at least one of the flash memory cells is evaluated during the precharge cycle after the bitlines have attained the preset voltage. Each of the flash memory cells undergoing evaluation is connected with a unique bitline.
In addition, each page buffer in the flash memory device additionally may comprise a latch and a transistor connected with both the latch and ground. The method according to the first aspect of the invention further comprises grounding one side of the latch contained in at least each page buffer connected with every bitline being charged via the transistor. The grounding occurs prior to the bitlines attaining the preset voltage.
A second aspect of the present invention is also directed towards a method for precharging a flash memory device. The flash memory device comprises a plurality of core cell blocks containing flash memory cells, a plurality of page buffers and a plurality of bitlines. Each of the page buffers is in communication with all of the core cell blocks via a unique bitline. The method includes charging at least one of the bitlines to a preset voltage during a portion of a precharge cycle. Additionally, the preset voltage may be maintained for the duration of the precharge cycle. The logic state of at least one of the flash memory cells may be evaluated during an evaluation cycle. The evaluation cycle occurs after the precharge cycle. Each of the flash memory cells undergoing evaluation is connected with a unique bitline.
Additionally in the second aspect of the invention, each page buffer in the flash memory device comprises a latch and a transistor connected with both the latch and ground. The method according to the first aspect of the invention further comprises grounding one side of the latch contained in at least each page buffer connected with every bitline being charged via the transistor. The grounding occurs prior to the evaluation cycle.
A third aspect of the present invention is directed towards a precharging mechanism for a flash memory device. The precharging mechanism comprises at least one core cell, at least one memory element contained within each core cell, at least one page buffer, at least one address line and at least one bitline. Each memory element is addressed by one of the address lines. Each bitline has a bitline voltage and data is produced on at least one of the bitlines by a unique memory element connected with the bitline.
In the third aspect of the invention, each of the page buffers also contains a precharging mechanism operative to precharge at least one bitline to a predetermined voltage. The bitline is charged via a first current before a predetermined memory element contained in at least one core cell is addressed. A second current is present in the bitline after the predetermined voltage has been attained.
In a further embodiment of the third aspect of the present invention, each page buffer further comprises a latch and a transistor. The transistor is connected with both one side of the latch and ground and serves to ground one side of the latch prior to the predetermined voltage being attained.
It is therefore a primary advantage of the present invention to increase the speed of response of the flash device by decreasing the charging time associated with the evaluation cycle. The decrease in the charging time may be accomplished by using either a precharge mechanism or method to precharge the bitline before reading the data from a particular word line.
The following figures and detailed description of the preferred embodiments will more clearly demonstrate these and other objects and advantages of the invention.
REFERENCES:
patent: 4173766 (1979-11-01), Hayes
patent: 5280446 (1994-01-01), Ma et al.
patent: 5349221 (1994-09-01), Shimoji
patent: 5748529 (1998-05-01), Lee
patent: 5748536 (1998-05-01), Kwon et al.
patent: 5768192 (1998-06-01), Eitan
patent: 5825686 (1998-10-01), Schmitt-Landsiedel et al.
patent: 5847998 (1998-12-01), Van Burkirk
patent: 5867430 (1999-02-01), Chen et al.
patent: 5986929 (1999-11-01), Sugiura et al.
patent: 6055188 (2000-04-01), Takeuchi et al.
patent: 6058042 (2000-05-01), Nobukata
patent: 2 157 489 (1985-10-01), None
patent: WO 99/07000 (1999-02-01), None
Hollmer Shane
Le Binh Q.
Yang Andrew
Advanced Micro Devices Inc
Brinks Hofer Gilson & Lione
Mai Son
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