Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Bump leads
Reexamination Certificate
1999-06-10
2001-07-17
Graybill, David E. (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Bump leads
C257S738000, C257S778000, C257S783000
Reexamination Certificate
active
06262483
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to a semiconductor chip module and method for manufacturing the same, more particularly to a semiconductor chip module that has a relatively short signal transmission path between semiconductor chips and that occupies a relatively small amount of board space.
2. Description of the Related Art
With the growing trend toward faster processor chips, the tolerable time delay for signal access to a peripheral memory chip has become increasingly shorter. Therefore, it is imperative for the designer to find a way to shorten the signal transmission path between a processor chip and a peripheral memory chip. On the other hand, with the growing need for a larger memory capacity, the number of memory chips on a printed circuit board is on the rise. However, the area of the printed circuit board is limited. Thus, as to how a large number of memory chips can be incorporated onto a printed circuit board with a minimum impact on board penalty has become a major concern of designers.
SUMMARY OF THE INVENTION
Therefore, the main object of the present invention is to provide a semiconductor chip module and a method for manufacturing a semiconductor chip module, wherein the signal transmission path between semiconductor chips can be shortened to minimize time delay.
Another object of the present invention is to provide a semiconductor chip module and a method for manufacturing a semiconductor chip module, wherein a large number of memory chips can be incorporated onto a printed circuit board without requiring a substantial increase in the size of the latter.
According to one aspect of the present invention, a semiconductor chip module comprises:
a first semiconductor chip having a pad mounting surface with a plurality of first bonding pads provided thereon;
a dielectric tape layer having opposite first and second adhesive surfaces, the first adhesive surface being adhered onto the pad mounting surface of the first semiconductor chip, the dielectric tape layer being formed with a plurality of holes at positions registered with the first bonding pads to expose the first bonding pads, each of the holes being confined by a wall that cooperates with a registered one of the first bonding pads to form a contact receiving space;
a plurality of conductive contacts placed in the contact receiving spaces, respectively; and
a second semiconductor chip having a chip mounting surface adhered onto the second adhesive surface of the dielectric tape layer, the chip mounting surface being provided with second bonding pads that are bonded to the conductive contacts to establish electrical connection with the first bonding pads.
According to another aspect of the present invention, a method for manufacturing a semiconductor chip module comprises:
adhering a first adhesive surface of a dielectric tape layer onto a pad mounting surface of a first semiconductor chip, the dielectric tape layer being formed with a plurality of holes at positions registered with first bonding pads provided on the pad mounting surface to expose the first bonding pads, each of the holes being confined by a wall that cooperates with a registered one of the first bonding pads to form a contact receiving space;
placing a plurality of conductive contacts in the contact receiving spaces, respectively; and
adhering a chip mounting surface of a second semiconductor chip onto a second adhesive surface of the dielectric tape layer opposite to the first adhesive surface, and bonding second bonding pads provided on the chip mounting surface to the conductive contacts to establish electrical connection with the first bonding pads.
Preferably, the second adhesive surface is provided with a heat-curable adhesive having a curing point that is lower than melting point of the conductive contacts. Thus, adhering of the second semiconductor chip onto the dielectric tape layer and bonding of the second bonding pads to the conductive contacts can be performed simultaneously via a heat curing operation such that the chip mounting surface is already adhered onto the second adhesive surface prior to melting of the conductive contacts.
REFERENCES:
patent: 5468681 (1995-11-01), Pasch
patent: 6057598 (2000-05-01), Payne et al.
patent: 6100594 (2000-08-01), Fukui et al.
Graybill David E.
Ladas & Parry
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