Semiconductor integrated circuit and driving method using...

Details Semiconductor integrated circuit and driving method using... Semiconductor integrated circuit and driving method using...

1998-06-26

2001-07-10

Wamsley, Patrick (Department: 2819)

Coded data generation or conversion

Analog to or from digital conversion

Analog to digital conversion

C341S120000

Reexamination Certificate

active

06259393

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor integrated circuit and a driving method thereof and, more particularly, to a semiconductor integrated circuit suitably applicable to a successive comparison A-D converter, and a driving method thereof.
2. Related Background Art
With present development of digital signal processing, the A-D converters for converting an analog signal to a digital signal are important technology and the A-D converters of various methods (hereinafter referred to as AD converters) have been developed heretofore. Particularly in high-speed applications, the mainstream converters are flash AD converters wherein there are comparison voltages corresponding to all levels of a quantization range and in the case of N-bit conversion, the converter has (2N−1) comparators for concurrent comparison and encoding. Since the number of comparators was large, such AD converters were not suitable for applications to portable remote terminals and the like requiring low power consumption. Therefore, the successive comparison AD converters, which are AD converters of low power consumption, have widely been and are used.
FIG. 1
is a block diagram to show an example of the successive comparison AD converter. An analog signal to be converted is applied to input terminal
50
to be input to a (+) input terminal of comparator
51
. Connected to a (−) input terminal of the comparator
51
is an output of D-A converter
54
whose input bit is set by successive comparison register
53
and which generates a comparison analog voltage.
A control circuit
52
sets a value of the successive comparison control register
53
, based on a result of the comparator
51
, to control the output of the DA converter
54
. In the successive comparison AD converter, the analog signal input is successively converted bit by bit from MSB (Most Significant Bit) into a digital code. Let us consider successive comparison of N bits. In response to a control signal from the control circuit
52
, the successive comparison register sets 1 at the N-th bit, which is the MSB, and 0 to the other bits. This code is applied to the DA converter
54
to be converted into an analog comparison signal Vda. In this case, the analog comparison signal Vda is generated as a voltage equal to a half of the entire quantization range, which is compared with the analog input signal Vin applied to the input terminal
50
. When Vin>Vda, the output from the comparator
51
becomes “H” to be sent to the control circuit
52
. Receiving “H”, the control circuit
52
rewrites the data in the successive comparison register so as to set 1 to the lower bit (MSB-
1
) while maintaining 1 in the MSB, which is the bit having been compared so far, and then sends the result to the DA converter
54
. In this case, the MSB bit is determined to be 1 and the next comparison operation is carried out with setting 1 in the (MSB-
1
) bit. When Vin<Vda, the output of the comparator
51
is “L” and is sent to the control circuit
52
. Receiving “L”, the control circuit
52
rewrites the data in the successive comparison register so as to change the MSB, which is the bit having been compared so far, from 1 to 0 and set 1 in the lower bit (MSB-
1
), and sends the result to the DA converter
54
. In this case, the MSB bit is determined to be 0, and then the next comparison operation is carried out with setting 1 in the (MSB-
1
) bit. This operation is repeated while performing the comparison and register setting in order from the upper bit to the lower bit, so that the data of the successive comparison register finally becomes a binary code resulting from the A-D conversion of the analog input signal Vin applied to the input terminal
50
.
For configuring a successive comparison AD converter with many bits, however, the successive comparison AD converter shown in
FIG. 1
was not suitable because the number of bits of the DA converter
54
for generating the analog comparison voltage needed to be the same as the number of bits of the AD converter, resulting in increasing the circuit scale and in turn increasing power consumption. The conversion accuracy of the AD converter of the successive conversion method was mainly dependent upon errors of the DA converter
54
, and the increase in the number of bits degraded the accuracy of DA converter
54
. As a result, the AD convertor came to lack monotonicity and make a coding error.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a semiconductor integrated circuit that can perform highly accurate A-D conversion by a simple circuit configuration, and a driving method thereof.
Another object of the present invention is to provide a semiconductor integrated circuit that can perform the A-D conversion operation with low power consumption and in high integration without increase in the circuit scale, and a driving method thereof.
Still another object of the present invention is to provide a semiconductor integrated circuit comprising: signal amplifying means (
2
,
10
in
FIG. 2
) capable of switching a gain, preferably, to 1 or 2; arithmetic processing means (
7
,
9
in
FIG. 2
) connected to an input side of the signal amplifying means, the arithmetic processing means carrying out a subtraction process of a reference voltage from a signal input thereto to output a result of the subtraction process, or outputting the signal input thereto without performing the subtraction process; changeover means (
8
in
FIG. 2
) whose one changeover terminal is connected to a signal input terminal (
1
in
FIG. 2
) and whose other changeover terminal is connected to an output side of sample hold means (
5
,
6
in FIG.
2
), a common terminal of the changeover means being connected to an input side of the arithmetic processing means; a comparator (
3
in
FIG. 2
) connected to an output side of the signal amplifying means, the comparator comparing an output from the signal amplifying means with the reference voltage (
12
in
FIG. 2
) to binarize the output; and switch means (
11
in
FIG. 2
) connecting the output side of the signal amplifying means to an input side of the sample hold means;
wherein the arithmetic processing means (
7
,
9
in
FIG. 2
) carries out a changeover (a changeover of
9
in
FIG. 2
) between performing the subtraction process of the reference voltage from the signal input thereto to output the result and outputting the signal input without performing the subtraction process, based on an output from the comparator (
3
in FIG.
2
).
Another object of the present invention is to provide a semiconductor integrated circuit comprising: signal amplifying means (
2
in
FIG. 4
) capable of switching a gain, preferably, to 1 or 2 and capable of performing a changeover between performing a subtraction process of a reference voltage from a signal input thereto to output a result of the subtraction process and outputting the signal input thereto without performing the subtraction process; changeover means (
8
in
FIG. 4
) whose one changeover terminal is connected to a signal input terminal (
1
in
FIG. 4
) and whose other changeover terminal is connected to an output side of sample hold means (
5
,
6
in FIG.
4
), a common terminal of the changeover means being connected to an input side of the signal amplifying means; a comparator (
3
in
FIG. 4
) connected to an output side of the signal amplifying means, the comparator comparing an output from the signal amplifying means with the reference voltage (
12
in
FIG. 4
) to binarize the output; and switch means (
11
in
FIG. 4
) connecting the output side of the signal amplifying means to an input side of the sample hold means; wherein the signal amplifying means (
2
in
FIG. 4
) carries out the changeover (a changeover of
9
in
FIG. 4
) between performing the subtraction process of the reference voltage from the signal input thereto to output the result and outputting the signal input thereto without performing the subtraction process, based o

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