Low voltage high speed multiplexer and latch

Details Low voltage high speed multiplexer and latch Low voltage high speed multiplexer and latch

1999-03-19

2001-04-03

Lam, Tuan T. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Gating

Converging with plural inputs and single output

C327S408000

Reexamination Certificate

active

06211722

ABSTRACT:

TECHNICAL FIELD
This invention is related to a high speed bipolar logic circuit with a decreased node capacitance providing increased switching speed.
BACKGROUND OF THE INVENTION
Multiplexers and latches are the fastest electronic components in a fiber-optic communication system. Currently, high-speed electronics for these types of systems are limited by the speed of these critical components. Component speed depends on the speed with which the logic circuit can be switched from one state to another and switching speed is dependent on, among other things, the logic voltage swing and the internal capacitances of the circuit.
Shown in
FIG. 1
a
is a conventional high-speed ECL circuit
10
configured for use as a multiplexer. The output voltage appears between nodes X and Y, as voltage drops across resistors
12
,
14
. The current through each resistor follows alternative paths to the ground (V
EE
). For example, the current from node X may flow into pull-down resistor
28
through either transistors
16
and
24
or transistors
20
and
26
. The state of the CK input to transistor
24
and the inverse {overscore (CK)} input to transistor
26
determines which path is connected to resistor
28
, and thereby determines whether the A data input or B data input controls the output.
Each current path includes two transistors in a stacked pair configuration, i.e., the emitter terminal of one transistor is connected to the collector terminal of another transistor. Because each base-emitter junction of a transistor introduces a voltage drop in silicon technology of about 0.8 volts, the power supply voltage must be substantially greater than 1.5 volts if deep saturation of these transistors is to be avoided. This problem is exacerbated in many III-V technologies, where the turn-on voltage is often higher than that in silicon.
FIG. 1
b
is a known low-voltage logic gate circuit
30
which addresses the problem of the relatively high-voltage power supply required to drive stacked transistors and is described in U.S. Pat. No. 5,289,055 to Razavi. The circuit
30
is configured so that no path between V
CC
and V
EE
includes a stacked pair of transistors. Transistors
32
and
34
form a differential pair having A and {overscore (A)} inputs which are connected to respective transistor bases. Similarly, transistors
36
and
38
form a differential pair having B and {overscore (B)} inputs connected to respective transistor bases. The emitters of the first differential pair are electrically connected to each other at node M, and the emitters of the second differential pair are connected at node N. Nodes M and N are then electrically connected to V
EE
through resistors
40
and
42
, respectively.
Transistors
32
and
34
are alternately enabled and disabled by clock signal CK applied to the base of transistor
44
. When transistor
44
is conducting, the voltage at node M is pulled high, decreasing the magnitude of B
BE
at the A and {overscore (A)} inputs. This disables the effect of the A data inputs by preventing transistors
32
and
34
from being activated. Similarly, the effect of the B data inputs applied to transistors
36
and
38
is alternately enabled and disabled by signal {overscore (CK)} applied to the base of transistor
46
to alter the voltage at node N. The output voltage is taken between nodes X and Y and is dependent on which data input is enabled by the CK signal and the value of that data signal.
Because no path for electric current between V
CC
and V
EE
includes a stacked pair of transistors, a power supply voltage (e.g., V
CC
−V
EE
) as low as 1.5 volts in conventional silicon technology can be used. However, the emitters of three separate transistors are connected to each of nodes M and N, and each transistor contributes a non-negligible amount of additional node capacitance. Thus, the switching speeds of the clocked transistors
44
,
46
and the associated data transistors are limited by the combined capacitances at node M and N of the emitters of three separate transistors.
SUMMARY OF THE INVENTION
According to the invention, a high-speed and low-voltage logic circuit, such as a multiplexer or latch, is provided which can operate at speeds in excess of 40 GBit/s using power supplies as low as 4.25 volts, typical for InP-based heterojunction bipolar technology. Instead of gating both a data input and its complement with a single clock-driven transistor, as is in conventional circuits, each data input, whether normal or a data complement, is gated by a separate clock-driven transistor. The data and clock transistors are configured as emitter-coupled differential pairs. Because the clock transistor in each differential pair is connected to only one data transistor, the corresponding node capacitance is reduced when compared with conventional circuit arrangements, thus providing increased switching speed.
In one embodiment of the invention, four such differential pairs are provided. Two differential pairs are driven by the positive clock signal and receive a first data input and its complement. The other two pairs are driven by the inverse clock signal and receive a second data signal and its complement. The voltage signal levels for data and clock signals are interleaved to allow the selected differential pairs to be correctly turned on and off. The output data corresponds to the first or second data input as selected by the value of the clock signal and thus the circuit functions as a multiplexer. Cross-coupling the data outputs to the inputs of the second data signal provides a latch circuit.
According to the invention, a variety of other digital circuits can be configured using this split-clock differential pair arrangement to provide high speed and low voltage operation. By appropriate preconditioning of the output and input signals, such as by level shifting or signal amplification, other logic functions can also be realized.


REFERENCES:
patent: 4900954 (1990-02-01), Franz et al.
patent: 4963767 (1990-10-01), Sinh
patent: 5289055 (1994-02-01), Razavi
patent: 5402013 (1995-03-01), Friedrich
patent: 355127773 (1980-10-01), None

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