Static information storage and retrieval – Powering
Reexamination Certificate
2000-02-22
2001-07-03
Nguyen, Viet Q. (Department: 2818)
Static information storage and retrieval
Powering
C365S227000, C365S189110, C365S191000, C365S189090, C327S536000
Reexamination Certificate
active
06256250
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a power supply circuit for supplying a voltage to a memory cell during a data writing process, and relates in particular to a power supply circuit for improving a voltage boosting speed.
2. Description of the Prior Art
In order to provide increased integration when manufacturing integrated circuits, the sizes of circuit elements are constantly being reduced. One such conventional integrated circuit is a power supply circuit that is especially employed to generate a voltage for writing, erasing or reading data, and to supply the voltage to individual peripheral circuits and to a memory cell.
FIG. 6
is a block diagram showing a conventional power supply circuit. In the conventional power supply circuit, connected to the anode (node NA
1
) of a boosting capacitor Cboost
1
is a boosting driver circuit
11
, and connected to its cathode (node NC
1
) are a pre-charge circuit
12
and a boosting circuit
13
. Also connected to the node NC
1
are various voltage generation circuits and a decoder. When data reading, writing or erasing is performed for a memory cell, a voltage equal to or higher than power supply voltage Vcc is supplied by the node NC
1
to the voltage generation circuits and to the decoder. The voltage generation circuits control and generate, for example, verification voltages, compaction voltages or drain voltages.
FIG. 7
is a circuit diagram showing the boosting driver circuit
11
, which is part of the conventional power supply circuit. A NAND circuit
14
is provided in the boosting driver circuit
11
to process the potentials input at terminals S
11
and S
12
, and to output the result to the node NA
1
.
In the pre-charge circuit
12
, a P-channel transistor is connected to the node NC
1
and the power source Vcc. When the boosting circuit
13
and the boosting driver circuit
11
are inactive, the power voltage Vcc is supplied to the node NC
1
by the pre-charge circuit
12
.
FIG. 8
is a timing chart showing the memory cell reading process performed by the conventional power supply circuit.
In the thus arranged conventional power supply circuit, the boosting circuit
13
and the boosting drive circuit
12
are inactive before the memory cell reading process is initiated, and, as is shown in
FIG. 8
, constant pre-charging of the node NC
1
with the voltage Vcc is performed by the pre-charge circuit
12
. As is further shown in
FIG. 8
, at the terminals S
11
and S
12
the potentials are Vcc, and at the node NA
1
the potential is the ground potential Vss.
When the reading of data from a memory cell actually begins, as is shown in
FIG. 8
the potential at the terminal S
11
goes to Vss while the potential at the terminal S
12
goes to Vcc, and the pulse Vcc is applied to the node NA
1
. That is, after the potential has been changed from Vss to Vcc, the boosting driver circuit
11
supplies it to the node NA
1
. Therefore, as is shown in
FIG. 8
, the boosting capacitor Cboost
1
raises the potential at the node NC
1
to Vboost
1
(>Vcc), which is supplied to the gate of the memory cell by the decoder, and data are read from the memory cell. At this time, the boosting circuit
13
is inactive.
In the data writing or erasing performed in the memory cell, a voltage Vcp (>Vcc) is generated by the boosting circuit
13
and is supplied to the node NC
1
. At this time, since the power source voltage Vcc is supplied to the terminals S
11
and S
12
, the voltage at the node NA
1
is fixed at Vss. When data is to be written, the voltage Vcp supplied to the node NC
1
is transmitted to the gate of the memory cell.
However, in the conventional power supply circuit, when the boosting circuit
13
is activated the boosting capacitor Cboost
1
imposes a capacitive load on the boosting circuit
13
, and the boosting speed of the voltage Vcp is reduced. And when the boosting speed is reduced, the time required to write and erase data in a memory cell is extended, and the consumption of current is increased.
BRIEF SUMMARY OF THE INVENTION
OBJECT OF THE INVENTION
It is, therefore, one object of the present invention to provide a power supply circuit that can facilitate the rapid writing and erasing of data, and that can reduce the consumption of current.
SUMMARY OR THE INVENTION
To achieve the above object, according to the present invention, a power supply circuit, which generates a read voltage and a write voltage for a memory cell at a first node, comprises:
a boosting circuit, for boosting a voltage at the first node to a first voltage when a writing operation is initiated;
a capacitor, one end of which is connected to the first node and the other end of which is connected to a second node;
a driver circuit, for changing the voltage at the first node from a second voltage to a third voltage when a reading operation is initiated; and
a connection circuit, for electrically connecting the first node to the second node when the writing operation is initiated.
REFERENCES:
patent: 5262999 (1993-11-01), Etoh et al.
patent: 5526313 (1996-06-01), Etoh et al.
patent: 5610863 (1997-03-01), Yamad
patent: 6121821 (2000-09-01), Miki
patent: 6137732 (2000-10-01), Inaba
patent: 401097165A (1989-04-01), None
patent: 1-140698 (1989-09-01), None
patent: 411353899A (1999-12-01), None
Japanese Office Action dated Apr. 18, 2000, with partial translation.
McGinn & Gibb PLLC
NEC Corporation
Nguyen Viet Q.
LandOfFree
Power supply circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Power supply circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Power supply circuit will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2529589