Method of modifying the current conducted by the access...

Details Method of modifying the current conducted by the access... Method of modifying the current conducted by the access...

2000-12-08

2001-09-11

Le, Vu A. (Department: 2824)

Static information storage and retrieval

Powering

C365S201000, C365S189090, C327S512000

Reexamination Certificate

active

06288966

ABSTRACT:

FIELD OF THE INVENTION
The invention relates generally to static-random-access-memory (SRAM) devices and, more particularly, to SRAM's utilizing a four transistor design.
DESCRIPTION OF THE BACKGROUND
To meet customer demand for smaller and more power efficient integrated circuits (ICs), manufacturers are designing newer ICs that operate with lower supply voltages and that include smaller internal subcircuits such as memory cells. Many ICs, such as memory circuits or other circuits such as microprocessors that include onboard memory, include arrays of SRAM cells for data storage. SRAM cells are popular because they operate at a higher speed than dynamic-random-access-memory (DRAM) cells, which must be periodically refreshed.
FIG. 1
is a circuit diagram of a conventional 6-transistor (6-T) SRAM cell
10
, which can operate at a relatively low supply voltage, for example 1.5V-3.3V, but which is relatively large. A pair of NMOS access transistors
12
and
14
allow complementary bit values D and {overscore (D)} on digit lines
16
and
18
, respectively, to be read from and to be written to a storage circuit
20
of the cell
10
. The storage circuit
20
includes NMOS pull-down transistors
22
and
26
, which are coupled in a positive-feedback configuration with PMOS pull-up transistors
24
and
28
, respectively. Nodes A and B are the complementary inputs/outputs of the storage circuit
20
, and the respective complementary logic values at these nodes represent the state of the cell
10
. For example, when the node A is at logic 1 and the node B is at logic 0, then the cell
10
is storing a logic 1. Conversely, when the node A is at logic 0 and the node B is at logic 1, then the cell
10
is storing a logic 0. Thus, the cell
10
is bistable, i.e., the cell
10
can have one of two stable states, logic 1 or logic 0.
In operation during a read of the cell
10
, a word-line WL, which is coupled to the gates of the transistors
12
and
14
, is driven to a voltage approximately equal to Vcc to activate the transistors
12
and
14
. For example purposes, assume that Vcc=logic 1=5V and Vss=logic 0=0V, and that at the beginning of the read, the cell
10
is storing a logic 0 such that the voltage level at the node A is 0V and the voltage level at the node B is 5V. Also, assume that before the read cycle, the digit lines
16
and
18
are equilibrated to approximately Vcc−Vt. Therefore, the NMOS transistor
12
couples the node A to the digit line
16
, and the NMOS transistor
14
couples the node B to the digit line
18
. For example, assume that the threshold voltages of the transistors
12
and
14
are both 1V, then the transistor
14
couples a maximum of 4V from the digit line
18
to the node B. The transistor
12
, however, couples the digit line
16
to the node A, which pulls down the voltage on the digit line
16
enough (for example, 100-500 millivolts) to cause a sense amp (not shown) coupled to the lines
16
and
18
to read the cell
10
as storing a logic 0.
In operation during a write, for example, of a logic 1 to the cell
10
, and making the same assumptions as discussed above for the read, the transistors
12
and
14
are activated as discussed above, and logic 1 is driven onto the digit line
16
and a logic 0 is driven onto the digit line
18
. Thus, the transistor
12
couples 4V (the 5V on the digit line
16
minus the 1V threshold of the transistor
12
) to the node A, and the transistor
14
couples 0V from the digit line
18
to the node B. The low voltage on the node B turns off the NMOS transistor
26
, and turns on the PMOS transistor
28
. Thus, the inactive NMOS transistor
26
allows the PMOS transistor
28
to pull the node A up to 5V. This high voltage on the node A turns on the NMOS transistor
22
and turns off the PMOS transistor
24
, thus allowing the NMOS transistor
22
to reinforce the logic 0 on the node B. Likewise, if the voltage written to the node B is 4V and that written to the node A is 0V, the positive-feedback configuration ensures that the cell
10
will store a logic 0.
Because the PMOS transistors
24
and
28
have low on resistances (typically on the order of a few kilohms), they can pull the respective nodes A and B virtually all the way up to Vcc often in less than 10 nanoseconds (ns), and thus render the cell
10
relatively stable and allow the cell
10
to operate at a low supply voltage as discussed above. But unfortunately, the transistors
26
and
28
cause the cell
10
to be relatively stable and allow the cell
10
to operate at a low supply voltage as discussed above. But unfortunately, the transistors
26
and
28
cause the cell
10
to be approximately 30%-40% larger tan a 4-transistor (4-T) SRAM cell, which is discussed next.
FIG. 2
is a circuit diagram of a conventional 4-T SRAM cell
30
, where elements common to
FIGS. 1 and 2
are referenced wit like numerals. A major difference between the 6-T cell
10
and the 4-T cell
30
is that the PMOS pull-up transistors
24
and
28
of the 6-T cell
10
are replaced with conventional passive loads
32
and
34
, respectively. For example, the loads
32
and
34
are often polysilicon resistors. Otherwise the topologies of the 6-T cell
10
and the 4-T cell
30
are the same. Furthermore, the 4-T cell
30
operates similarly to the 6-T cell
10
. Because the loads
32
and
34
are usually built in another level above the access transistors
12
and
14
and the NMOS pull-down transistors
22
and
26
, the 4-T cell
30
usually occupies much less area an the 6-T cell
10
.
Additional, complex steps are required to form the load elements
32
and
34
such that 4-T cells present the usual complexity versus cost tradeoff. The high resistance values of the loads
32
and
34
can substantially lower the stability margin of the cell
30
as compared with the cell
10
. Thus, under certain conditions, the cell
30
can inadvertently become monostable or read unstable instead of bistable Also, the cell
30
consumes more power than the cell
20
because there is always current flowing from Vcc to Vss through either the load
32
and the NMOS transistor
26
or the load
34
and the NMOS transistor
22
. In contrast, current flow from Vcc to Vss in the cell
20
is always blocked by one of the NMOS/PMOS transistor pairs
22
/
24
and
26
/
28
. Efforts to eliminate load elements
32
and
34
have lead to the development of a load-less four transistor SRAM cell as shown in FIG.
3
.
FIG. 3
is a circuit diagram of a conventional load-less 4-T SRAM cell, where elements common to
FIGS. 2 and 3
are referenced with like numerals. The difference between the load-less cell
36
and the cell
30
is the elimination of load elements
32
and
34
and the replacement of NMOS transistors
12
and
14
with PMOS transistors
38
and
40
, respectively.
With the load-less 4-T SRAM cell of
FIG. 3
, like all SRAM cells, leakage currents and/or subthreshold currents are generate by transistors
22
and
26
when in the off state, and one will always be in the off state. To prevent the cell
36
from spontaneously changing state, the transistors
38
and
40
must source sufficient load current from the digit lines
16
and
18
, respectively, to offset the leakage and subthreshold currents. The needed load current can vary over many orders of magnitude due to temperature and process variations. However, the load current cannot be too large because the cumulative (along the digit lines
16
and
18
) load current needs to be significantly less than the cell current for proper noise margin for proper operation of the sense amps.
Wide temperature variations resulting from cold-data retention testing and burn-in testing are also causes of wide variations in leakage and subthreshold currents, thereby causing wide variations in the load current that must be sourced by transistors
38
and
40
. Such testing, coupled with normal process variations, sense amp margin requirements, as well as yield requirements (e.g., read/write stability requi

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