Static information storage and retrieval – Addressing
Reexamination Certificate
2000-01-28
2001-07-10
Nelms, David (Department: 2818)
Static information storage and retrieval
Addressing
C365S230080, C365S236000
Reexamination Certificate
active
06259646
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to memory devices and more particularly, the present invention relates to decoding and counting of memory addresses in such devices.
BACKGROUND OF THE INVENTION
The performance of computer systems has improved dramatically due to a rapid growth in computer architecture design and particularly in the performance of computer memory. However, access times to the data residing in computer memory has not improved at a corresponding rate.
FIG. 1
is a typical memory device. In particular,
FIG. 1
illustrates memory device
100
that includes control
38
, latch
18
, row decode
22
, counter
26
, column decode
30
, memory array
12
, input/output (I/O) logic and latches
34
and write drivers and data sense amplifiers
52
. Memory device
100
can be coupled to an external microprocessor or memory controller for memory accessing and is used to store data which is accessed via data bus
10
. It will be appreciated by those skilled in the art that additional circuitry and control signals can be provided.
For example, for a write operation, an address along with data is inputted to memory device
100
through address bus
16
and data bus
10
, respectively. The data on data bus
10
is written into memory array
12
at the address given by address bus
16
. In particular, row address strobe (/RAS) signal
14
, column address strobe (/CAS) signal
24
, write enable (/WE) signal
36
and output enable (/OE) signal
42
, which are coupled to control
38
, latch
18
, counter
26
and I/O logic and latches
34
, control the input and output to and from memory array
12
, as is known in the art. Based on these control signals, the address is decoded by row decode
22
and column decode
30
through latch
18
and counter
26
, respectively, thereby activating the memory cells that are being written to using write drivers and data sense amplifiers
52
, as is known in the art. The data on data bus
10
is then written to these activated memory cells of memory array
12
through I/O bus
32
.
Disadvantageously, due to the low latency (i.e., zero clocks) of the write path and the setup requirements of writing to memory array
12
, the logic that decodes the column address (i.e., column decode
30
) used for enabling the proper write drivers can be in the critical path of memory device
100
.
Moreover, for embodiments of memory device
100
that includes compare circuitry to determine whether a page count is complete during a read or write operation, conventional circuitry compares a decoded version of the memory address to a reference version of such a memory address that is also decoded. Disadvantageously, this decode-to-decode compare circuitry requires many gates to perform the compare, thereby decreasing the speed of such a compare and also increasing the size of memory devices using such circuitry. Accordingly, there is a need for a reduction of the criticality of the decode logic path of such memory devices as well as a faster and smaller compare circuitry to determine whether a page count is complete during read and write operations of such devices. For these and other reasons there is a need for the present invention.
SUMMARY OF THE INVENTION
The above-mentioned problems with access times of memory devices and other problems are addressed by the present invention and will be understood by reading and studying the following specification. Structures and methods are described which accord improved benefits for accessing of memory devices.
In particular, improved methods and structures are provided that reduce the criticality of a decode logic path for a memory device by moving the decode logic circuitry prior to the counter circuitry for a memory device, thereby enabling the decoding of the write drivers and data sense amplifiers during the setup time of a load path of the memory device. Further, improved methods and structures are provided that enable the determination of when a page count is complete in a memory array of a memory device with smaller and faster circuitry than current conventional count complete circuitry.
Embodiments of a structure include a memory device that comprises a decode logic circuitry that decodes an address. The memory device also includes a counter circuitry coupled to the decode logic circuitry that generates a counter value based on the decoded address. Embodiments of the present invention also includes methods, other structures as well as systems incorporating such structures all formed according to the methods provided in this application.
Additionally, other embodiments of a structure include a compare circuit that determines whether a page count is complete in a memory structure. The compare circuit includes a holding circuitry that includes a number of latches for holding an encoded version of a memory address. The compare circuit also includes a multiplexing circuitry coupled to the holding circuitry. The multiplexing circuitry receives the encoded version of the memory address from the holding circuitry and a decoded version of the memory address from a decoder, such that the multiplexing circuitry uses the encoded version to select one bit of the decoded version of the memory address to determine whether the page count is complete for the memory structure.
These and other embodiments, aspects, advantages, and features of the present invention will be set forth in part in the description which follows, and in part will become apparent to those skilled in the art by reference to the following description of the invention and referenced drawings or by practice of the invention. The aspects, advantages, and features of the invention are realized and attained by means of the instrumentalities, procedures, and combinations particularly pointed out in the appended claims.
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Le Thong
Micro)n Technology, Inc.
Nelms David
Schwegman Lundberg Woessner & Kluth P.A.
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