Static information storage and retrieval – Addressing – Including particular address buffer or latch circuit...
Reexamination Certificate
2000-05-01
2001-06-12
Nelms, David (Department: 2818)
Static information storage and retrieval
Addressing
Including particular address buffer or latch circuit...
C365S185080
Reexamination Certificate
active
06246634
ABSTRACT:
TECHNICAL FIELD
The present invention relates to an integrated memory circuit having a plurality of flash memory arrays and at least one SRAM memory array and more particularly with the integrated memory circuit having an internal data and address bus to transfer signals between the memory arrays and an external data and address bus to receive and transfer signals from the memory arrays to external circuitry to the memory circuit.
BACKGROUND OF THE INVENTION
SRAM memory arrays are well known in the art. They are characterized by a fast write time and a fast read time. However, they suffer from the disadvantage of being volatile and low density. Flash memory arrays are also well known in the art. They offer the advantage of high density as well as non-volatility. However, they suffer from the disadvantage of low erase and programming speed as well as low read speed. Heretofore, the prior art teaches the use of an SRAM memory array having as many storage locations as a flash memory array to “shadow” the memory array. Data would be stored to and read from the SRAM memory array. During the time that the memory array is not being accessed, the contents of the SRAM memory array would be transferred to the accompanying flash memory array for long-term non-volatile storage. It should be recognized, however, that in such an arrangement, should access be required from the SRAM memory array during the time that it is transferring its contents to the flash memory array, the entire memory circuit would not be accessible by the external environment. In such an event, the memory circuit would be busy.
Further, another disadvantage of this prior art memory device is that a large amount of memory is devoted to the SRAM which is low density since there has to be as many SRAM memory cells as there are flash memory cells. Accordingly, it is desirable to reduce the number of SRAM memory cells and yet at the same time provide higher periods of accessibility for the entire memory circuit.
SUMMARY OF THE INVENTION
An integrated memory circuit comprises a first array of non-volatile memory cells and a second array of volatile memory cells. A first address bus and a first data bus carries a first address signal and a first data signal, respectively, from sources external to the circuit to and from the circuit. The memory circuit also has a second address bus and a second data bus for carrying a second address signal and a second data signal, respectively, which are internal to the circuit. Each of the first and second arrays of memory cells further comprises an access circuit for connecting the array of memory cells to the first address bus or the second address bus and to connect the array of memory cells to the first data bus or the second data bus. Finally, the integrated memory circuit comprises a control circuit which is responsive to data signals supplied on said first data bus and to a certain address signal supplied on the first address bus for transferring data from said first array of non-volatile memory cells to said second array of volatile memory cells along said second data bus.
REFERENCES:
patent: 5590073 (1996-12-01), Arakawa et al.
See Specification of Application. Specifically, p. 2 second paragraph.
Gray Cary Ware & Freidenrich LLP
Nelms David
Silicon Storage Technology, Inc.
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