Multiplex communications – Communication techniques for information carried in plural... – Combining or distributing information via time channels
Reexamination Certificate
1998-09-04
2001-07-24
Ngo, Ricky (Department: 2735)
Multiplex communications
Communication techniques for information carried in plural...
Combining or distributing information via time channels
C370S528000, C375S367000
Reexamination Certificate
active
06266349
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method and an apparatus for detecting frames in a data stream including frames and flags for use in data transmission and receipt system such as portable telephones, and in particular a method and an apparatus for distinguishing regular flags used for detecting the frames from a bit stream which forges the pattern of the regular flags.
2. Description of Prior Art
There has been published a technical document “Universal Communication Interface” (image data media society bulletin Vol. 51, No. 2, p. 174-182 (1997), which teaches HDLC (High-Level Data Link Control) system as a scheme of transmitting a plurality of frames each including variable-length data. The HDLC employs a pattern “01111110” as flags indicative of boundaries between the frames, which are hereinafter referred to as the HDLC flags. Under the HDLC system, the transmission apparatus inserts HDLC flags between frames to be sent to the receipt apparatus, thus transmitting a data stream including the frames and the HDLC flags. The receipt apparatus detects the HDLC flags to provide the boundaries between the frames. Hence, use of the HDLC flags establishes synchronization of the frames.
A bit stream laid in a frame, however, might forge the same pattern as that of the HDLC flags, or might act as a false HDLC flag, which causes the receipt apparatus to recognize the bit stream as a boundary between a frame and an adjacent frame. This wrong operation is hereinafter referred to as the flag emulation.
To avoid the flag emulation, the HDLC system employs the zero bit insertion. As shown in
FIG. 11
, to implement the zero bit insertion, a common transmission apparatus incorporates the zero bit insertion circuit
1000
and the flag insertion circuit
1001
. Into the data transmission apparatus are fed a frame stream including a plurality of frames and a frame synchronization signal denoting the boundaries between the frames. A common receipt apparatus incorporates the flag detection circuit
2000
, the flag deletion circuit
2001
, and the zero bit deletion circuit
2002
. From the data receipt apparatus are output a frame stream including a plurality of frames and a frame synchronization signal denoting the boundaries between the frames, both of which corresponds to the frame stream and the frame synchronization signal of the data transmission apparatus.
In the transmission apparatus, the zero bit insertion circuit
1000
inserts a zero bit “0” into the incoming frame stream and the flag insertion circuit
1001
inserts HDLC flags between the frames of the frame stream. In the receipt apparatus, the flag detection circuit
2000
detects those HDLC flags, the flag deletion circuit
2001
deletes these HDLC flags, and the zero bit deletion circuit
2002
deletes the zero bit “0” inserted by the zero bit insertion circuit
1000
.
More definitely, pursuant to the zero bit insertion scheme, upon occurrence of one zero bit and continues five one bits “011111” in a frame, a zero bit “0” is inserted immediately thereafter. As shown in
FIG. 12
, for example, a bit stream including the same pattern “01111110” as that of the HDLC flags experiences the zero insertion to change into “011111010”. This can avoid presence of a bit stream the pattern of which is identical with that of the HDLC flags. Hence, the data stream having no bit stream with the pattern “01111110” reaches the receipt apparatus. After establishing the frame synchronization using the regular HDLC flags, the receipt apparatus deletes the zero bit laid after the continuous five one bits to regenerate the bit stream “01111110”. Thus, even though there exists a bit stream “01111110” in a frame of the frame stream of the transmission apparatus, the data receipt apparatus does not misunderstand the bit stream “01111110” as a HDLC flag, that is to say, the data receipt apparatus can avoid a flag emulation.
As shown
FIG. 13
, if there occurs a bit error in a HDLC flag itself during transmission over a propagation path to force the HDLC flag into acting as an arbitrary bit stream, a frame and another frame both of which are adjacent to the deformed HDLC flag appears to be connected to each other via the HDLC flag. The deformed HDLC flag thus disables the receipt apparatus from detecting the boundary between those frames.
As shown in
FIG. 14
, if there arises in a frame a bit stream having the same pattern as that of the HDLC flags during transmission over a propagation path likewise, the bit stream rises a flag emulation, which divides into two frame portions the frame where the bit stream is laid.
For the purpose of solving the above problems, there has been applied a pseudo random sequence as the flag for frame detection in lieu of the HDLC flag, which is hereinafter referred to as the PN sequence. Further, a flag pursuant to the PN sequence is hereinafter referred to as the PN flag. The PN sequence has a correlation property that is indicative of a correlation value between a bit stream and another bit stream, as shown in FIG.
15
. The correlation value is extremely large when all the bits in the former bit stream and all the bits in the latter bit stream completely coincides with each other. To the contrary, the correlation value is small even when there exists a gap of one bit between the former bit stream and the latter bit stream.
Therefore, repetitive comparison of a reference flag having the pattern of the PN flags with a data stream through shifting the reference fag bit-by-bit enables detection of the PN flags. For example, it is assumed that the reference flag laid at the position No. 2 coincides with a PN flag in the data stream while the reference flags laid at the position No. 1 and No. 3 are respectively being shifted by one bit in comparison with the reference flag of the position No. 2. The former reference flag gives an extremely large correlation value, but the latter reference flags give a small correlation value. Accordingly, employing such a PN sequence to compare correlation values with a predetermined threshold value enables detection of regular PN flags, which establishes a frame synchronization based upon those detected PN flags.
As shown in
FIG. 16
, a typical data transmission apparatus of the PN sequence incorporates the flag insertion circuit
3000
, and also a typical data receipt apparatus incorporates the flag correlation detection circuit
4000
, and the flag deletion circuit
4001
. Into the data transmission apparatus are fed a frame stream and a frame synchronization signal similarly to the data transmission apparatus of the HDLC system. In such a transmission apparatus, the flag insertion circuit
3000
inserts PN flags between the frames of the incoming frame stream in synchronization with the frame synchronization signal, whereby the data stream involving the PN flags reaches the data receipt apparatus. In the receipt apparatus, the flag correlation detection circuit
4000
detects the boundaries between the frames based upon the correlation values between the data stream and the reference flag, and the flag deletion circuit
4001
deletes the PN flags from the data stream. This provides a frame stream and a frame synchronization signal similarly to the data receipt apparatus of the HDLC system. In summary, except for the zero bit insertion/deletion and the flag detection, the data transmission and receipt apparatus using the PN flags function similarly to the data transmission and receipt apparatus using the HDLC flags, as shown in FIG.
17
.
If, however, there is laid in a frame of the frame stream a bit stream having the pattern of the PN flags in the data transmission apparatus, the receipt apparatus recognizes the bit stream as a PN flag. As a result, a flag emulation is yielded, which the frame including the bit stream is divided into two frame portions as shown in FIG.
18
. Since the flag emulation disables regeneration of the frame including such a bit stream in the data receipt apparatus, there is employed the ARQ (Automatic Repeat R
Fukui Kiyoshi
Nonaka Masato
Ngo Ricky
Oki Electric Industry Co. Ltd.
Rabin & Champagne, P.C.
Tran Phuc
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