Remote register hierarchy accessible using a serial data line

Details Remote register hierarchy accessible using a serial data line Remote register hierarchy accessible using a serial data line

1999-03-30

2001-01-16

Nelms, David (Department: 2818)

Static information storage and retrieval

Plural shift register memory devices

C365S219000, C365S221000

Reexamination Certificate

active

06175518

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to digital integrated circuits, and more particularly to an apparatus and method for accessing numerous remote registers on an integrated circuit chip using a minimum of interconnect traces.
BACKGROUND
FIG. 1
illustrates a system of registers
100
implemented on an integrated circuit chip according to the teachings of U.S. Pat. No. 5,644,609 (hereinafter “the '609 patent”). The '609 patent issued Jul. 1, 1997, to John Bockhaus et al., is assigned to Hewlett-Packard Company, and is hereby incorporated by reference in its entirety. System of registers
100
includes staging register block
102
and a series of
32
remote register blocks
104
-
114
. A serial data line
116
exits staging register block
102
from a serial data output, propagates through each of the 32 remote register blocks in the series, and then reenters staging register block
102
at a serial data input. A control signal line
118
exits staging register block
102
from a control signal output and propagates through each of the
32
remote register blocks to the last remote register block in the series. Each of remote register blocks
104
-
114
contains a single remote data register that is associated with a unique address from ADR
0
to ADR
31
, as shown.
In operation, staging register block
102
generates a header containing a it 5-bit address for selecting one of the
32
remote registers to read data from or write data to, and also containing a R/{overscore (W)} bit for indicating whether a read or a write operation is desired. Using control line
118
and serial data line
116
, staging register block
102
propagates this header through the series of remote register blocks so that each remote register block may determine if it has been selected. When a remote register block determines if it has been selected, it shifts data from its remote register onto serial data line
116
in the event the header indicated that a read operation was requested, or it shifts data into its remote register in the event the header indicated that a write operation was requested. Each remote register block in the series represents a one-bit delay in the loop.
Staging register block
102
is coupled to a microprocessor general purpose register or registers
101
via a parallel data path
120
. Special microprocessor instructions are used to read from and write to the remote registers distributed throughout the chip. For writes, one microprocessor instruction is used to load the write data into general purpose microprocessor register
101
, and another microprocessor instruction (having as its operand the address of the remote register to be written) is executed to shift the address and data through the series of remote register blocks to effect the write. For reads, a microprocessor instruction (having as its operand the address of the remote register to be read) is executed to shift a header containing the desired read address through the series of remote register blocks and back into staging register block
102
. Because the selected remote register block will have placed the desired data onto the serial data line in response to the header, the read data will have been clocked into the staging register block on the serial data line at the completion of the read operation.
The teachings of the '609 patent represent an advancement of the art with regard to reducing the number of interconnect traces required to access remote registers on an integrated circuit chip. Further advancements are needed, however, if the system disclosed in the '609 patent is to be extended in an efficient manner. Specifically, it would be desirable to be able to access more than
32
remote registers via staging register block
102
and remote register blocks
104
-
114
. The '609 patent teaches, at column 7, lines 9-13, that this may be done “simply by adding to or subtracting from the number of bits used in the header address field (bits AD
0
-
4
).” Such a solution would entail at least three significant drawbacks: First, for each bit added to the header address field, an additional clock would be required for every read or write shifting operation. Second, for each remote register block added to the series, an additional bit of latency would be added to the chain. Third, every remote register block in the series—not just the newly-added remote register blocks beyond the original
32
—would have to be redesigned to accommodate the new address field length in the header.
It is therefore an object of the present invention to provide a mechanism for accessing more than 32 remote registers via series
104
-
114
without changing the length of the header address field (bits AD
0
-
4
), without adding one bit of latency for every register beyond the original
32
, and without redesigning each of the remote register circuitry blocks in the series.
SUMMARY OF THE INVENTION
The invention includes numerous aspects, each of which contributes to achieving the above-stated objectives.
In one aspect, hierarchical secondary registers may be implemented on an integrated circuit chip as follows: Plural primary nodes are configured in series along a serial data line, each of the plural primary nodes individually selectable according to a primary address presented on the serial data line. A hierarchical one of the plural primary nodes includes: plural secondary registers, each of the plural secondary registers individually selectable according to a secondary address presented on the serial data line; circuitry for communicating data from a selected one of the plural secondary registers to the serial data line during a read operation; and circuitry for communicating data from the serial data line to the selected one of the plural secondary registers during a write operation.
Method steps used to write data to one of the secondary registers may include: presenting a primary address on the serial data line, the primary address for selecting a target primary node out of the plural primary nodes configured in series along the serial data line; presenting a secondary address on the serial data line, the secondary address for selecting a target secondary register out of the plural secondary registers associated with the target primary node; and presenting data on the serial data line to be written into the target secondary register.
Method steps used to read data from one of the secondary registers may include: at a first location, presenting a primary address on the serial data line, the primary address for selecting a target primary node out of the plural primary nodes configured in series along the serial data line; at the first location, presenting a secondary address on the serial data line, the secondary address for selecting a target secondary register out of the plural secondary registers associated with the target primary node; and, at a second location, presenting data from the target secondary register on the serial data line.
In another aspect, hierarchical tertiary registers may be implemented on an integrated circuitry chip as follows: Plural primary nodes are configured in series along a serial data line, each of the plural primary nodes individually selectable according to a primary address presented on the serial data line. A hierarchical one of the plural primary nodes includes plural secondary nodes, each of the plural secondary nodes individually selectable according to a secondary address presented on the serial data line. At least one of the plural secondary nodes includes: plural tertiary registers, each of the plural tertiary registers individually selectable according to a tertiary address presented on the serial data line; circuitry for communicating data from a selected one of the plural tertiary registers to the serial data line during a read operation; and circuitry for communicating data from the serial data line to the selected one of the plural tertiary registers during a write operation.
Method steps used to write data to one of the tertiary registers may include

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