Write driver using continuous damping network to reduce...

Details Write driver using continuous damping network to reduce... Write driver using continuous damping network to reduce...

1997-06-02

2001-04-10

Faber, Alan (Department: 2753)

Dynamic magnetic information storage or retrieval

General processing of a digital signal

Head amplifier circuit

C360S068000, C327S538000, C327S310000

Reexamination Certificate

active

06215607

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a magnetic head read/write preamplifier within a magnetic storage system, and particularly to a write driver circuit within the read/write preamplifier having improved switching speed, improved rise/fall time, reduced write current ringing, and reduced asymmetry.
In magnetic data storage systems, a magnetic read/write head is operable to write binary data, representing ones and zeros, onto a magnetic medium such as a magnetic tape or disc. The head uses an inductive coil to generate magnetic fields, which form magnetic patterns on the medium representing the ones and zeros. The orientation of the patterns depends on the direction of electrical current flow through the inductive coil, so that writing the binary data entails selectively changing, or reversing, the direction of current flow through the head. Changing the direction of current flow through the coil is the function of a write driver.
The write driver includes a drive circuit, coupled to the head, and a control circuit for operating the drive circuit in response to control data signals. Conventionally, the drive circuit is configured as an H-switch, which has a pair of forward switches and a pair of reverse switches. (The term H-switch stems from the H-shaped arrangement of the four switches and the head in electrical schematics.) The control circuit is conventionally responsive to a pair of complementary, or differential, control data signals to selectively open and close the forward and reverse switches of the H-switch, thereby changing the direction of current through the head to write a specific bit pattern on the magnetic medium.
The major components of the write driver are usually formed from transistors, which serve as switches. For example,
FIG. 1
shows a typical write driver
10
coupled to a head
11
that includes an inductive coil L
H
. Write driver
10
includes an H-switch drive circuit
12
and a differential control circuit
14
. The H-switch drive circuit, connected between opposite supply terminals such as V
CC
and ground, includes four drive transistors Q
1
-Q
4
, two head terminals
16
and
18
, and a write current source I
W
. Transistors Q
1
and Q
4
serve as forward switches, and transistors Q
2
and Q
3
serve as reverse switches.
Differential control circuit
14
comprises control transistors Q
5
and Q
6
, pull-up resistors R
1
and R
2
, and pre-driver control current source I
D
, and operates the forward and reverse switches Q
1
-Q
4
in response to write control signals at write control inputs V
X
and V
Y
. Specifically, when input V
Y
is a higher voltage than input V
X
, control circuit
14
closes, or turns on, control transistor switch Q
5
, and opens, or turns off, control transistor switch Q
6
. This arrangement turns on the forward switches Q
2
and Q
3
and turns off the reverse switches Q
1
and Q
4
. As a result, current I
W
flows from V
CC
through switch Q
2
, head
11
from terminal
18
to terminal
16
, and switch Q
3
into the ground of the circuit. Conversely, when input V
X
is at a higher voltage than input V
Y
control circuit
14
turns on control transistor switch Q
5
and turns off control transistor switch Q
6
, thereby turning on the reverse switches and turning off the forward switches. This directs write current I
W
through switch Q
1
, head
11
from terminal
16
to terminal
18
, and switch Q
4
into the ground of the circuit. Thus, changing the relative voltage levels at inputs V
X
and V
Y
changes the direction of write current flow through head
11
.
In practice, the write driver of
FIG. 1
suffers from two problems. First, its constituent transistors have inherent switching speed limitations which inhibit the write driver and head from writing data as quickly and as densely as is necessary in high performance data storage systems. Second, the current flowing through the head immediately following a change in the direction of current flow tends to “overshoot” the desired value of write current, resulting in an additional delay for the write current to settle at its desired value after a transition.
The transistors forming the write driver suffer from switching limitations. Unlike ideal switches, transistors have inherent structural, or parasitic, capacitances which prevent them from instantaneously opening (turning off) or closing (turning on). These capacitances charge or discharge while opening or closing the transistor switch, and thus slow or delay the opening and closing of the transistor switch. The delays in opening and closing not only limit how fast bits are written but ultimately how closely the bits are spaced on a magnetic medium. The closeness of the bits, which is known as bit density, is a factor in the data capacity of a magnetic medium.
One particular aspect of this switching limitation or problem concerns transistors Q
1
-Q
4
, the four drive transistors of the H-switch drive circuit. These transistors have a larger surface area than control circuit transistors Q
5
and Q
6
, enabling them to conduct the relatively large write current necessary for operating the write head. Larger transistors generally have larger inherent capacitances, which require more time to charge and discharge than do smaller capacitances. Thus, within the write driver, the four H-switch drive transistors Q
1
-Q
4
are a significant factor limiting switching speed and bit density.
To alleviate the switching limitations of the H-switch drive transistor, artisans have sought to increase the capacity of control circuit
14
to rapidly charge and discharge the larger inherent capacitances of these transistors and thereby reduce their turn-on and turn-off times. There are several known approaches for increasing the current charging the drive transistors and thereby reducing their turn-on times.
One approach entails increasing current flow through resistors R
1
and R
2
, known as pull-up resistors. Unfortunately, increasing the current flow through resistors R
1
and R
2
also reduces the voltage change across the write head, known as head swing, which in turn reduces switching speed. Head swing determines the rate of change of current in the write head, which in turn determines how fast current in the write head itself can actually start, stop, and reverse direction in writing individual data bits. Reducing head swing therefore reduces switching speed. This approach is especially inadequate in low-voltage applications where any reduction in head swing significantly reduces switching speed.
A second approach entails connecting separate NPN emitter-follower circuits between the respective pull-up resistors R
1
and R
2
and the respective bases, or control nodes, of drive transistors Q
1
and Q
2
. More particularly, an NPN emitter-follower includes an NPN transistor with its base connected to pull-up resistor R
1
, its collector coupled to the positive voltage supply terminal V
CC
. and its emitter coupled to the base of transistor Q
1
and to the ground terminal through a pull-down resistor. When activated, the NPN transistor drives an emitter current into the base of upper drive transistor Q
1
that rapidly charges the capacitance of transistor Q
1
and thus accelerates its turn-on. When deactivated, the NPN transistor allows the capacitance of upper drive transistor Q
1
to passively discharge through the pull-down resistor to the ground terminal. The counterpart emitter-follower between resistor R
2
and the control node of upper drive transistor Q
2
operates similarly. Unlike the first approach of increasing current flow in the pull-up resistors, the NPN emitter-follower circuits improve the turn-on times of the upper drive transistors without diminishing headswing. However, this approach is also inadequate because it improves only the turn-on times, and not the turn-off times of the upper drive transistors.
A third approach entails connecting separate PNP pull-down transistor circuits between the respective control nodes of transistors Q
3
and Q
4
and the ground terminal of the circuit. A w

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