Static information storage and retrieval – Powering
Reexamination Certificate
2000-02-03
2001-06-12
Le, Vu A. (Department: 2824)
Static information storage and retrieval
Powering
C365S229000, C365S063000
Reexamination Certificate
active
06246625
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device, and, specifically to a structure for reducing current consumption in a semiconductor device including a logic gate consisting of CMOS transistors (complementary insulated gate type field effect transistors) without affecting operating characteristics thereof. More specifically, the present invention relates to a structure for reducing subthreshold current of a semiconductor memory device such as a DRAM (Dynamic Random Access Memory).
2. Description of the Background Art
A CMOS circuit has been well known as a semiconductor circuit of which power consumption is extremely small.
FIG. 60
shows a structure of a general CMOS inverter.
Referring to
FIG. 60
, the CMOS inverter includes a p channel MOS transistor (insulated gate type field effect transistor) PT provided between a power supply node
1900
receiving one operating power supply voltage Vcc and an output node
1901
and receiving at its gate an input signal IN; and an n channel MOS transistor NT provided between the other power supply node
1902
receiving the other operating power supply voltage Vss (generally, ground potential) and output node
1901
and receiving at its gate the input signal IN. There is a load capacitance C at output node
1901
. When input signal IN is at a low level, p channel MOS transistor PT turns on, n channel MOS transistor NT turns off, load capacitance C is charged through p channel MOS transistor PT, and an output signal OUT attains to the power supply voltage level Vcc. When charging of the load capacitance C is completed, source and drain of p channel MOS transistor PT come to have the same potential, and thus the transistor PT turns off. Therefore, at this time, current does not flow, and power consumption is negligible.
When input signal IN is at a high level, p channel MOS transistor PT turns off, n channel MOS transistor NT turns on, and load capacitance C is discharged to the level of the other power supply potential Vss through n channel MOS transistor NT. When the discharge is completed, the source and drain of n channel MOS transistor NT come to have the same potential, and thus the transistor NT turns off. Therefore, in this state also, power consumption is negligible.
A drain current IL flowing through a MOS transistor can be represented by a function of a gate-source voltage of the MOS transistor. When the absolute value of the gate-source voltage becomes larger than the absolute value of the threshold voltage of an MOS transistor, a large drain current flows. Even when the absolute value of the gate-source voltage becomes not higher than that of absolute value of the threshold voltage, the drain current is not completely reduced to 0. This drain current flowing under such a voltage is referred to as subthreshold current which is exponentially proportional to the gate-source voltage.
FIG. 61
shows subthreshold current characteristic of an n channel MOS transistor. Referring to
FIG. 61
, the abscissa represents gate-source voltage VGS, and the ordinate represents logarithmic value of drain current IL. In
FIG. 61
, linear regions of lines I and II each represent the subthreshold current. The threshold voltage is defined as the gate-source voltage providing a prescribed current in this subthreshold current region. For example, in MOS transistor having the gate width (channel width) of 10 &mgr;m, the gate-source voltage causing a drain current flow of 10 mA is defined as the threshold voltage.
FIG. 61
represents the prescribed current I
0
and the threshold voltages VT
0
and VT
1
.
As the MOS transistor has been made smaller and smaller, the power supply voltage Vcc decreases in accordance with the scaling rule. Therefore, the absolute value Vth of the threshold voltage of the MOS transistor must be decreased similarly in accordance with the scaling rule in order to improve performance of the MOS transistor. In the CMOS inverter shown in
FIG. 60
, for example, assume that the power supply voltage Vcc is 5 V and the threshold voltage Vth of n channel MOS transistor NT is 1 V. When input signal IN changes from 0 V to a value larger than 1 V, a large drain current flow is generated, starting discharging of load capacitance C. On the other hand, when the power supply voltage Vcc is lowered to 3 V, for example, while maintaining the threshold voltage Vth at the same value, the load capacitance C can be discharged with large current only when the input signal IN exceeds 1 V to turn on the n channel MOS transistor NT. More specifically, when the power supply voltage Vcc is 5 V, discharge of capacitive load starts at ⅕ of the amplitude of the input signal IN. Meanwhile, when the power supply voltage Vcc is 3 V, discharge of capacitive load C starts at ⅓ of the amplitude of input signal IN. Namely, input/output response characteristic is degraded, and hence high speed operation cannot be ensured. Therefore, the absolute value Vth of the threshold voltage needs to be scaled similarly down as the power supply voltage. However, as shown in
FIG. 61
, when the threshold voltage VT
1
is lowered to the threshold voltage VT
0
, the subthreshold current characteristic changes from that represented by the line I to that of the line II. Accordingly, the subthreshold current when the gate voltage is 0 V (Vss level) rises from IL
1
to IL
0
, increasing current consumption. Thus, difficulty is encountered in scaling down the absolute value Vth of the threshold voltage in the similar manner as the power supply voltage and in realizing superior operating characteristics, especially high speed operation.
Structures for suppressing subthreshold current without degrading high speed operation characteristic have been disclosed in pages
47
and
48
, and in pages
83
and
84
of 1993
Symposium on VLSI Circuit, Digest of Technical Pacers
, by Horiguchi et al. and Takashima et al., respectively.
FIG. 62
shows a structure of a power supply line disclosed by Horiguchi et al. in the above described article.
FIG. 62
shows, as an example of a CMOS circuit, n cascade connected CMOS inverters f
1
to fn. Each of inverters f
1
to f
4
has the same structure as that shown in FIG.
60
.
In a path for supplying one operating power supply voltage, a first power supply line
1911
is connected to the first power supply node
1910
receiving power supply voltage Vcc, and a second power supply line
1912
is arranged parallel to the first power supply line
1911
. First power supply line
1911
is connected to second power supply line
1912
by means of a high resistance Ra. Parallel to the resistance Ra, a p channel MOS transistor Q
1
for selectively connecting first power supply line
1911
and second power supply line
1912
in response to a control signal &phgr;c is provided. Between the first and second power supply lines
1911
and
1912
, a capacitor Ca having a relatively large capacitance for stabilizing the potential of second power supply line
1912
is provided.
A transmission path of the other power supply voltage Vss (ground potential:0 V) includes a third power supply line
1921
connected to a second power supply node
1920
receiving the other power supply voltage (hereinafter simply referred to as the ground voltage) Vss, and a fourth power supply line
1922
arranged parallel to the third power supply line
1921
. Between the third and fourth power supply lines
1921
and
1922
, a high resistance Rb is provided, and parallel to the resistance Rb, there is provided an n channel MOS transistor Q
2
for selectively connecting the third power supply line
1921
and the fourth power supply line
1922
in response to a control signal &phgr;s. Between the third and fourth power supply lines
1921
and
1922
, a capacitor Cb having large capacitance for stabilizing the potential of the fourth power supply line
1922
is provided.
Inverters f
1
, f
3
, . . . of odd-numbered stages have one operating power supply node (power supply node receiving a high potential) connected to
Arimoto Kazutami
Tsukude Masaki
Yamagata Tadato
Le Vu A.
McDermott & Will & Emery
Mitsubishi Denki & Kabushiki Kaisha
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