Computer graphics processing and selective visual display system – Plural physical display element control system – Display elements arranged in matrix
Reexamination Certificate
1997-09-24
2001-04-03
Saras, Steven (Department: 2675)
Computer graphics processing and selective visual display system
Plural physical display element control system
Display elements arranged in matrix
C345S087000, C345S090000, C345S098000
Reexamination Certificate
active
06211849
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a liquid crystal display device having a structure in which a plurality of liquid crystal pixels are arranged in matrix, and more specifically to a driving circuit for controlling voltages across these liquid crystal pixels to display an image.
An active matrix liquid crystal device generally includes a liquid crystal panel having a structure in which a liquid crystal layer is interposed between an array substrate and a counter substrate opposing thereto. Each of the array substrate and the counter substrate has a transparent glass plate used as a base material, and the liquid crystal layer has a liquid crystal composition filled in the space between the array substrate and the counter substrate. The array substrate includes a matrix array of pixel electrodes, scanning lines respectively formed along the rows of these pixel electrodes, signal lines respectively formed along the columns of these pixel electrodes, Thin Film Transistors (TFTS) respectively formed at positions close to the intersections of the scanning lines and the signal lines, and each serving as a switching element for electrically connecting one signal line to one pixel electrode in response to a selection signal from one scanning line, a scanning line driver for supplying the selection signal to the scanning lines and a signal line driver for supplying pixel data signals to the signal lines. In the liquid crystal display device, an image is displayed according to potential differences between the pixel electrodes and a common electrode.
For example, the signal line driver is composed of driver ICs arranged as shown in FIG.
1
. These driver ICs are connected to common bus lines including power lines VDD and GND, data lines DATA and control signal lines CNT. The driver ICs are arranged together with the common bus lines on a driver substrate provided near the periphery of a liquid crystal panel.
With regard to the liquid crystal display device having the above-described driver substrate, an increase in the dimensions of the frame region of the liquid crystal panel is required in order to obtain a larger size of screen or a higher resolution. Therefore, the COG (chip on glass) mount technique has been proposed in order to eliminate the drive substrate. According to this technique, thin film wirings are formed such as to be in contact with connection terminals exposed on the glass surface of the array substrate, and bare chips of driver ICs are soldered to the thin film wirings.
However, since a thin film wiring formed by the present COG mount technique, has a relatively high resistance, it is difficult to reduce the width of the wiring. This drawback causes an increase in the dimensions of the frame region of the liquid crystal panel. Further, generally, in the manufacture of liquid crystal panels, a plurality of array substrates are obtained from one glass plate. That is, circuit components of each array substrate are formed in one region which is obtained by partitioning the glass plate. In the case where all the thin film wirings are arranged within the array substrate, the area occupied by each array substrate is increased, and therefore a larger glass plate is required. In other words, the number of array substrates obtained from one glass plate is decreased. This results in an increase in the manufacturing cost for the liquid crystal panel. Alternatively, it is possible that only those of the thin film wirings which correspond to the common bus lines are formed on an external print wiring board; however the use of such a print wiring board may cause an increase in the manufacturing cost. For example, when the common bus line is elongated, it becomes difficult to transmit a signal at high speed since the elongation increases the parasitic capacitance which makes the waveform of the transmitted signal dull. Further, it becomes more likely that unnecessary radio waves are radiated from the common bus lines on the print wiring board. Consequently, shield layers or terminal resistances are additionally required to reduce the radiation of unnecessary radio waves.
Furthermore, it is possible that a plurality of driver ICs are formed on an array substrate by the COG mount technique, and thin films are formed as inter-module wirings between driver ICs, in order to prevent an increase in the dimensions of the frame region and in the manufacturing cost. The inter-module wirings serve to connect the driver ICs in cascade, and transmit signals via each driver IC. However, such a structure provides only a low signal transmission speed in which the clock frequency is set about 5 MHz. According to an experiment, the pulse width of a clock signal is decreased by 40 ns at worst each time the clock signal passes one driver IC. Therefore, in order to ensure a normal signal transmission, the number of driver ICs connected in cascade must be limited to about 10 at most.
BRIEF SUMMARY OF THE INVENTION
An object of the present invention is to provide a liquid crystal display device capable of achieving a larger screen size or a higher resolution, without unnecessarily increasing the dimensions of the frame region and the manufacturing cost.
According to the present invention, there is provided a liquid crystal display device which includes a liquid crystal panel having a matrix array of liquid crystal pixels, a plurality of scanning lines formed along rows of the liquid crystal pixels, and a plurality of signal lines formed along columns of the liquid crystal pixels; and a driving circuit for driving each of the scanning lines to select a row of the liquid crystal pixels and driving the signal lines to control voltages across the liquid crystal pixels of the selected row; wherein the driving circuit includes a signal line driver for sequentially driving the signal lines, and the signal line driver includes a plurality of driver ICs which are connected in cascade by inter-module wirings for transmitting at least a clock signal and a display signal and each of which sequentially supplies the display signal to a predetermined number of signal lines in synchronism with the clock signal, and each driver IC has a clock waveform shaping circuit for performing a clock signal waveform shaping by regulating a duty ratio of the clock signal to be output together with the display signal to a next stage.
In the liquid crystal display device, the clock signal waveform shaping circuit of each driver IC performs a clock signal waveform shaping by regulating the duty ratio of the clock signal. With this structure, it becomes possible to maintain a transmission capability regardless of an increase in the number of driver ICs. For example, in the case where a plurality of driver ICs are incorporated in a liquid crystal panel by the COG mount technique and they are connected in cascade by inter-module wirings of a high-resistance thin film,
a normal signal transmission can be attained even if the widths of the inter-module wirings are maintained small for avoiding an unnecessary increase in the dimensions of the frame region and the manufacturing cost of the liquid crystal panel.
Specifically, with the liquid crystal display device, a high signal transmission speed in which the clock frequency is set about 25 MHz to 65 MHz, can be achieved. Consequently, ten or more driver ICs can be connected in cascade so as to obtain a larger screen size or a higher resolution.
REFERENCES:
patent: 5164970 (1992-11-01), Shin et al.
patent: 5508728 (1996-04-01), Ishjima et al.
patent: 5543819 (1996-08-01), Farwell et al.
patent: 5585816 (1996-12-01), Scheffer et al.
patent: 5729316 (1998-03-01), Yamamura et al.
patent: 5751279 (1998-05-01), Okumura
patent: 5805003 (1998-09-01), Hsu
Sasaki Takeshi
Shimizu Kan
Kabushiki Kaisha Toshiba
Nelson Alecia D.
Pillsbury & Winthrop
Saras Steven
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