Semiconductor device manufacturing: process – Forming schottky junction
Reexamination Certificate
1999-10-29
2001-08-07
Bowers, Charles (Department: 2813)
Semiconductor device manufacturing: process
Forming schottky junction
C438S299000, C438S301000, C438S592000, C438S633000, C438S637000, C438S655000
Reexamination Certificate
active
06271106
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates, in general, to electronics, and more particularly, to methods of manufacturing semiconductor components.
For a semiconductor component to operate at high frequencies, the individual semiconductor devices, such as transistors, in the component must be able to operate at the high frequencies. For transistors to operate at high frequencies, the transistors must have, among other characteristics, short gate lengths, thin gate oxides, low gate resistance, and low parasitic gate capacitance. However, as the gate lengths are reduced, the gate resistance is inherently increased. Therefore, the gate resistance must be independently reduced.
Doped polysilicon is a material that is commonly used for gate electrodes in semiconductor transistors. To reduce the gate resistance, other electrically conductive materials having resistivities lower than that of doped polysilicon have been used to form the gate electrode. For example, tungsten silicide (WSi) has been used to either replace the entire traditional doped polysilicon gate or overlie the doped polysilicon gate. In either configuration, the WSi material may cause contamination problems resulting from the exposure of metals to the high anneal and activation temperatures.
The process where the traditional doped polysilicon gate is replaced entirely with a WSi gate is known in the art as a substitutional or back-filled gate process. The disadvantages of this process include the difficulty to manufacture small gate lengths, unpredictable changes in the work function of the transistor, and reliability problems at the interface between the metal gate and the semiconductor substrate.
The process where a metal layer overlies the doped polysilicon gate is known in the art as a “T”-gate process. The disadvantages of this process include limited scalability and increased parasitic capacitance, which lowers the operating frequency of the transistor.
Accordingly, a need exists for a robust and reliable method of manufacturing a semiconductor component that is capable of operating at high frequencies, has low gate resistance, and has short gate lengths.
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Grivna Gordon M.
Keating Richard A.
Ma Gordon C.
Bowers Charles
Hightower Robert F.
Motorola Inc.
Nguyen Thanh
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