Optics: measuring and testing – By alignment in lateral direction
Reexamination Certificate
1999-04-01
2001-08-07
Font, Frank G. (Department: 2877)
Optics: measuring and testing
By alignment in lateral direction
C356S400000
Reexamination Certificate
active
06271919
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device, and an associated alignment apparatus and alignment method, and more particularly it relates to a semiconductor device having an alignment mark that occupies a reduced surface area, and an alignment apparatus suitable for this semiconductor device that shortens the alignment time.
2. Description of the Related Art
In an alignment apparatus, when alignment marks that are formed in different base layers are used to perform alignment, in the case for example in which the alignment marks in the lowermost layer are used to perform alignment on the upper layer, because light used in the alignment passes through an interlayer film, an error occurs, this resulting in a reduction of alignment accuracy.
In the case in which the alignment marks that are formed on the upper layer are used to achieve positioning, that is, alignment, between a mask and a wafer, because of the cumulative errors that are included in each mark formed in the various process steps, there is a problem with alignment error.
In general, the selection of the ideal alignment marks to use is done at each alignment separately during the alignment steps.
For this reason, because alignment upper layers is performed by detecting the alignment marks formed in each layer and comparing this data so as to select the best alignment mark, the processing of alignment took a great deal of time in the past.
In the past, alignment marks, as shown in
FIG. 5
, have a width in the scanning direction of (diffraction grating distance X)×(diffraction grating number of lines), this being a width of 100 &mgr;m or greater, and because alignment is performed with a plurality of base layers, the alignment marks, as denoted by
21
and
22
in
FIG. 5
, inevitably occupy a considerable amount of surface area, this presenting the problem of hindering the achievement of a high degree of integration in the semiconductor integrated circuit.
Known alignment apparatuses are such as described, for example, in Japanese Unexamined Patent Publication (KOKAI) No.63-237522, Japanese Examined Patent Publication (KOKOKU) No.1-20529, Japanese Examined Patent Publication (KOKOKU) No.2-63287, Japanese Unexamined Patent Publication (KOKAI) No.64-25413, but these alignment apparatuses do not solve the above-described problems.
Accordingly, it is an object of the present invention to provide a solution to the drawbacks in the prior art as noted above, and in particular to provide a novel semiconductor device that alignment marks having a reduction in the surface area occupied on the semiconductor chip.
Another object of the present invention is to provide a novel alignment apparatus and alignment method that reduce the amount of time required to perform alignment.
SUMMARY OF THE INVENTION
In order to achieve the above-noted object, the present invention adopts the following basic technical constitution.
Specifically, an embodiment of the present invention is a semiconductor device having first alignment marks formed on a first layer and second alignment marks formed on a second layer that is different from said first layer, wherein said first alignment marks and said second alignment marks are disposed so as to be at a distance from each other that is approximately a diffraction grating distance.
A first aspect of an alignment apparatus according to the present invention is an alignment apparatus for a semiconductor device having first alignment marks formed on a first layer and second alignment marks formed on a second layer that is different from the first layer, this alignment apparatus having a first detection means for determining the position coordinates of the second alignment marks with respect to the first alignment marks, a second detection means for detecting the position skew (the position offset) between the first alignment marks and the second alignment marks, the position of which was detected by the first detection means, a third detection means that detects whether or not the distribution of the position skew detected by the second detection means is within a prescribed value, and an alignment execution means that performs alignment by selecting the second alignment marks when the third detection means detects that the distribution of skew is within the prescribed value.
In the second aspect of the present invention, the skew distribution is 3&sgr;.
The third aspect of an alignment apparatus according to the present invention is an alignment apparatus for a semiconductor device having first alignment marks formed on a first layer and second alignment marks formed on a second layer that is different from the first layer, this alignment apparatus having a first detection means for determining the position coordinates of the second alignment marks with respect to the first alignment marks, a second detection means for detecting the position skew between the first alignment marks and the second alignment marks, the position of which was detected by the first detection means, a third detection means that detects whether or not the distribution of the skew detected by the second detection means is within a prescribed value, a fourth detection means that corrects, from the position coordinates that are detected by the first detection means, the linear error component such as the position offset of the second alignment marks with respect to the first alignment marks, and detects the residual error thereof, a fifth detection means that detects whether or not the residual error detected by the fourth detection means is within a prescribed value, and an alignment execution means for performing alignment by selecting said second alignment marks in the case in which not only does said third detection means detect that said skew distribution is within its prescribed value, but also said fifth detection means detects that said residual error is within its prescribed value.
In the fourth aspect of the present invention, the second alignment marks are formed in a layer that is above the layer on which the first alignment marks are formed.
In the fifth aspect of the present invention, the first and second alignment marks are disposed so as to be approximately as close to each other as the diffraction grating distance.
The first aspect of an alignment method according to the present invention is an alignment method for a semiconductor device having first alignment marks formed on a first layer and second alignment marks formed on a second layer that is different from the first layer, this alignment method having a first step of determining the position coordinates of the second alignment marks with respect to the first alignment marks, a second step of detecting the position skew between the first alignment marks and the second alignment marks, the position of which was detected by first step, a third step of detecting whether or not the distribution of the position skew detected by the second step is within a prescribed value, a fourth step of performing alignment by selecting the second alignment marks when the third step detects that the position skew distribution was within the prescribed value.
The second aspect of an alignment method according to the present invention is an alignment method for a semiconductor device having first alignment marks formed on a first layer and second alignment marks formed on a second layer that is different from the first layer, this alignment method having a first step of determining the position coordinates of the second alignment marks with respect to the first alignment marks, a second step of detecting the position skew between the first alignment marks and the second alignment marks, the position of which was detected by first step, a third step of detecting whether or not the distribution of the position skew detected by the second step is within a prescribed value, a fourth step of correcting the linear error component such as the offset of the second alignment marks with respect to the first alignment m
Font Frank G.
NEC Corporation
Smith Zandra V.
Sughrue Mion Zinn Macpeak & Seas, PLLC
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