Electricity: conductors and insulators – Conduits – cables or conductors – Preformed panel circuit arrangement
Reexamination Certificate
1998-07-24
2001-06-12
Paladini, Albert W. (Department: 2841)
Electricity: conductors and insulators
Conduits, cables or conductors
Preformed panel circuit arrangement
C174S254000, C174S255000, C174S259000, C257S700000, C361S784000
Reexamination Certificate
active
06246014
ABSTRACT:
FIELD OF THE INVENTION
The invention relates to printed circuit assemblies and methods of manufacture therefor. More particularly, the invention relates to printed circuit assemblies and methods of manufacture thereof having controlled separations between conductive layers, and to printed circuit assemblies and methods of manufacture thereof in which multiple overlapping conductive layers are electrically interconnected.
BACKGROUND OF INVENTION
As the complexity and data processing speeds of electronic products continue to increase, the properties of the interconnecting circuitry which connects complex and high speed integrated circuit devices become more pronounced and must be carefully analyzed to ensure reliable circuit performance. Often, it is the increases in complexity and data processing speeds of integrated circuit devices that dictate performance improvements in the interconnecting circuitry to which the devices are mounted.
For example, the complexity of integrated circuit devices, and in particular the advent of surface mount technologies, dictate that greater densities of signal traces be packed into smaller packages to reduce costs and improve reliability. Signal trace widths and spacing has decreased to accommodate higher densities. Moreover, greater densities may be obtained with double- sided and multilayer printed wiring boards having multiple conductive layers that are typically electrically connected via conductive through holes.
Signal trace width and spacing, as well as through hole width and spacing, significantly impact the packaging density obtainable with interconnecting circuitry, and consequently, much development efforts are directed to interconnection technologies that decrease these minimum dimensions to permit greater packaging densities without compromising reliability or performance.
Some of these development efforts are related to the interlayer interconnection of overlapping conductive layers across dielectric layers, where it is desirable to decrease the size of the interconnects across the dielectric layers, while reducing manufacturing costs and complexities. For example, conductive through holes may be drilled and plated through multiple layers to form interlayer connections. However, drilled through holes occupy significant space on a printed circuit board, both because the through holes are formed through the entire board, regardless of which layers need be interconnected, and because most mechanical drilling processes are typically limited to holes with about 100 micron minimum diameters. Anisotropic adhesives are another alternative for forming interlayer connections; however, some anisotropic adhesives do not form pure metallurgical joints, and thus may suffer from a reliability standpoint. Further, they often require coverlayers to insulate nonconnected but overlapping conductive areas, thus increasing overall assembly thicknesses.
Therefore, a significant need continues to exist for a reliable interlayer interconnection technology which is compatible with the continuing drive to increase packaging densities in interconnecting circuitry.
As was also noted above, the data processing speeds obtainable with advanced high speed integrated circuit devices also dictate the required characteristics of the interconnecting circuitry used to connected such devices. Currently, integrated circuit devices may operate with a throughput in gigabits per second, resulting in pulse durations of less than a nanosecond and rise times in the picosecond range. Under these conditions, the conductors connecting these devices become active components in the circuits, both in terms of affecting propagation delays and impedance matching.
Propagation delays are affected by interconnecting circuitry such as printed circuit boards and assemblies principally as a result of the dielectric constant of the materials used in the circuitry. In particular, materials having low dielectric constants are desirable to use for minimizing any propagation delays, and thereby increasing the range of obtainable signal speeds within a circuit.
Impedance is principally the combination of resistance, capacitance and inductance which create electric and magnetic fields in a circuit. The impedance of a circuit is also called the characteristic impedance, as it depends solely on the characteristics of the materials used and their spatial relationship. Factors such as the dielectric constants of circuitry materials and lengths and widths of conductive signal traces primarily affect the characteristic impedance of an electronic circuit.
Matching the impedances of interconnecting circuitry with other electronic devices and connectors is important for ensuring signal integrity in a circuit. This is because, at high frequencies, signals may get reflected when impedance mismatches are present in a circuit. Such mismatches distort signals, increase rise times, and otherwise generate errors in data transmission. Consequently, impedance matching is often necessary to provide maximum power transfer between the connected electronic components and systems and to prevent signal reflections from forming along the signal paths.
As noted above, impedance in a printed circuit is directly related to the separation between signal traces separated by an insulating layer, as well as to the dielectric constant of the material in the insulating layer. One controlled impedance design is the surface microstrip configuration, where a signal trace opposes a ground plane, with no other overlapping conductive layers. Another is the stripline configuration, where a signal trace is sandwiched between a pair of ground planes.
Controlled impedance requires that both the dielectric constant of the insulating layer, and the separation between the signal traces, to be carefully controlled. For many conventional double-sided printed circuit assemblies, this may not be a significant problem because insulating substrates such as polymer films and hardboards can usually be manufactured with carefully controlled thicknesses and dielectric constants.
However, for many multilayer printed circuit assemblies (i.e., those with three or more conductive layers), impedance control is more difficult, typically because of the adhesives commonly used in the interlayer interconnection technologies that bond individual single- or double-sided boards together when forming such assemblies. A similar problem may also exist for some two layer boards, e.g., those with opposing single sided boards connected through adhesives.
The problem with such adhesives principally stems from the inability to control the separation between the opposing conductive layers during and after compression or lamination of the assembly, as most of the adhesives are designed to flow somewhat during lamination and fill in gaps between boards. As a result, it becomes difficult to obtain controllable separation throughout a printed circuit assembly. Additional problems may arise from imperfect or uncontrolled deposition of the conductive layers and any intervening coverlayers, resulting in varying thicknesses in these layers.
Another important concern with many multilayer printed circuit assemblies is planarity. In particular, it may be important to maintain controlled thicknesses of layers, even in non-impedance critical applications, so that outer surfaces of an assembly are substantially planar. This may be important, for example, when populating an assembly with integrated circuit and other electronic devices, since connecting pads on the assembly for mounting these devices should have similar elevations to ensure reliable connections there between. However, given the more compactible nature of insulating substrates and adhesives as compared to conductive material, lamination of such assemblies may induce non-planarity. Further, the effects are cumulative with the number of layers, and consequently, the effects may be more pronounced in thicker multilayer assemblies.
One type of interlayer interconnection technology used to bond together opposing conductive lay
Brueske Curtis B.
Honeywell International , Inc.
Paladini Albert W.
LandOfFree
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