Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2000-03-20
2001-05-08
Mai, Son (Department: 2818)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185180, C365S185240
Reexamination Certificate
active
06229734
ABSTRACT:
TECHNICAL FIELD
The present invention relates generally to nonvolatile semiconductor storage devices and more particularly to nonvolatile semiconductor storage devices having memory cells with alterable threshold voltages.
BACKGROUND OF THE INVENTION
Nonvolatile semiconductor storage devices can advantageously retain data values in the absence of power. This makes such devices highly desirable in portable electronic devices. Many types of nonvolatile semiconductor storage devices include memory cells having alterable threshold voltages. Such cells may be programmed to one particular threshold voltage, and erased to another. Among the types of storage devices that may include such cells are electrically erasable programmable read only memories (EEPROMs), including “flash” EEPROMs. Flash EEPROMs can include sectors having memory cells that can be simultaneously erased.
While nonvolatile semiconductor storage devices are desirable in portable devices, at the same time, the power supply levels of electronic devices continues to fall. While many types of integrated circuits can accommodate such lower power supply levels, such lower power supply levels can be more difficult to implement in nonvolatile devices.
To better understand the difficulties of reduced power supply levels in nonvolatile semiconductor storage devices, a conventional nonvolatile semiconductor storage device will be described.
FIG. 5
is a circuit diagram showing a conventional nonvolatile semiconductor storage device. The nonvolatile semiconductor storage device is designated by the general reference character
500
and is shown to include an array of memory cells, shown as M
01
to M
32
. Each memory cell (M
01
to M
32
) can be connected to a corresponding bit line (BL
0
to BLn) and word line (W
0
to Wn). Further, each memory cell (M
01
to M
32
) may include a control gate, a floating gate, and a substrate (with diffusion regions).
A read operation from memory cell M
01
will now be described. In a read operation, an applied address can result in row decoder
502
driving word line W
0
to a select potential while the remaining word lines, including Wn, are driven to a deselect potential. In addition, an address can result in a column decoder
504
activating a column select signal Y
0
while the remaining column select signals (Y
1
to Yn) are deactivated. Consequently, transfer gate Tr
0
can be enabled, connecting bit line BL
0
to sense amplifier input node DIG. A bit bias circuit
506
can bias input node DIG to a high potential. In a read operation, a power source switch
508
can connect sources and wells of the memory cells (M
01
to M
32
) to a ground potential (GND).
A read operation can also activate a reference select signal Yref and a reference word line signal Wref. In addition, a reference bit bias circuit
510
can bias a reference node DIGREF. This can result in a reference current Ir flowing through a reference memory cell MR.
If memory cell M
01
is programmed, its threshold voltage should be high enough that despite the select potential on word line W
0
, memory cell M
01
will remain essentially turned off. Thus, any current drawn by the cell (shown as Im) will be smaller in magnitude than the reference current Ir. This difference, Im<Ir, can be detected by a sense amplifier
512
as one logic value. If memory cell M
01
is erased, its threshold voltage should be sufficiently low enough that the select potential on word line W
0
will turn memory cell M
01
on. The current drawn by the cell (Im) will be greater in magnitude than the reference current Ir. This difference, Im>Ir, can be detected by a sense amplifier
512
as another logic value.
The above-described operation assumes that the memory cells (M
01
to M
32
) operate in an ideal fashion. However, in actual applications, the threshold voltages of erased memory cells may fall within a distribution. Further, memory cells at the lower end of the distribution can introduce a leakage current. That is, even when de-selected, such low voltage threshold memory cells may draw current on a biased bit line.
The problem of a low threshold voltage memory cells will now be described with reference to FIG.
5
. It will be assumed that memory cell M
01
is programmed while memory cell M
02
is erased, but has a low threshold voltage. In such a case, when memory cell M
01
is read, despite the fact that memory cell M
02
is deselected, memory cell M
02
will draw a leakage current. This leakage current by itself, or when combined with leakage current from other memory cells on bit line BL
0
, can result in Im being greater than Ir. Thus, sense amplifier
512
will erroneously read memory cell M
01
as an erased cell when it is in fact a programmed cell.
A low threshold voltage may vary according to processes and operating voltages. One example of a low threshold voltage is one volt.
As noted above, in most erase procedures, “flash” erase for example, erase threshold voltages can fall within a distribution. One such distribution is shown in FIG.
3
A. In
FIG. 3A
, the threshold voltages of erased cells essentially fall between a high erase threshold voltage of 2.5V and a low erase threshold voltage of 1V. That is, the erased cells have a threshold voltage range of about 1.5V. It can be very difficult, if not impossible, to avoid such distributions without adding additional time and/or cost and/or circuitry to an erase process. In some contexts, low threshold voltage memory cells are referred to as “overerased” memory cells.
The distribution of
FIG. 3A
may provide adequate functionality for nonvolatile semiconductor devices operating at a sufficiently high power supply voltage. In particular, provided a power supply potential is 2.5V or higher, the normal distribution of threshold voltages will not result in a significant number of low threshold voltage memory cells (e.g., cells having a threshold voltage of 1V or less). With a distribution such as that shown in
FIG. 3A
, a word line voltage of 2.5V can be used, as it will turn on an erased memory cell (as the erased cell threshold voltage distribution is below 2.5V), and not turn on a programmed memory cell (which is assumed to have a programmed threshold voltage greater than 2.5V).
A distribution such as that set forth in
FIG. 3A
can be problematic for lower power supply levels. For example, if a lower power supply level of 2V is used, the maximum word line voltage is 2V. Such a word line voltage may not generate sufficient current from an erased cell. In addition, or alternatively, data sensing may take much longer than desired.
One approach for maintaining sufficient sensing current could be to lower the maximum erase threshold voltage of a memory cell distribution. Such an approach is shown in FIG.
3
B. In
FIG. 3B
, the threshold voltages of erased cells have a high erase threshold voltage of 2V. However, because the erase threshold voltages retain the same distribution, the low erase threshold voltage is now 0.5 volts. It will be recalled, in this particular example, a low erase threshold voltage would be 1V or less. Thus, a distribution such as that of
FIG. 3B
can result in a large number of low threshold voltage memory cells. This can cause erroneous reading due to leakage current as described above.
The low threshold voltage of a memory cell may be adjusted by writing data to the memory cell. One of the many approaches includes a “soft” program operation, or the like. For example, if the location of a memory cell having a threshold voltage of less than 1V was known, the memory cell threshold voltage could be raised to 1V or higher by some sort of write operation.
Unfortunately, it is not possible to locate the position of a low threshold voltage memory cell with a conventional memory device arrangement. In particular, while it may be possible to know when a bit line draws too much leakage current, it is not possible to know which of the numerous deselected erased memory cells connected to the bit line is contributing to the leakage current.
One approach to narrowing the
Mai Son
NEC Corporation
Walker Darryl G.
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