CMOS voltage reference with post-assembly curvature trim

Details CMOS voltage reference with post-assembly curvature trim CMOS voltage reference with post-assembly curvature trim

1999-10-13

2001-04-17

Wong, Peter S. (Department: 2838)

Electricity: power supply or regulation systems

Self-regulating

Using a three or more terminal semiconductive device as the...

C323S316000, C323S907000

Reexamination Certificate

active

06218822

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to the field of CMOS voltage references, and more particularly to an apparatus and method for providing post-assembly curvature trim.
2. Description of the Related Art
Using a CMOS process to make a voltage reference has cost advantages over a precision-trimmed bipolar process. Problems with the accuracy and stability of CMOS devices must be overcome, however, in order to make a CMOS reference competitive in performance with bipolar references. Specifically, the lack of high-value stable and trimmable resistors presents a problem for circuit designers.
In order to adjust for variances in each circuit, voltage references are “trimmed” after manufacture in order to bring the output values within a specified range. This is generally accomplished by using lasers to etch away certain thin-film resistors (thereby increasing the resistance by decreasing the cross-sectional area). With proper design, most devices can be brought within the specified range using this technique. However, once the device (i.e. silicon die) is placed into a package, the mechanical stresses caused by the packaging can once again cause the circuit parameters to vary. Therefore, a competitive CMOS voltage reference must be designed such that the circuit may be “trimmed” after the final assembly of the die into a package.
One aspect of a voltage reference design requiring special consideration is “curvature correction.” Curvature correction has been the subject of many papers and patents over the past two decades. One of the earliest circuits is disclosed in U.S. Pat. No. 4,250,445 entitled “BAND-GAP VOLTAGE REFERENCE WITH CURVATURE CORRECTION” by Brokaw. As shown in
FIG. 1
, the disclosed circuit uses a diffused resistor Rb to add a low-order (temperature squared or T
2
) correction term to the reference output. The T
2
term is generated not by the resistor Rb itself (which is assumed to be linear) but by the combination of a positive temperature coefficient (TC) in the resistor Rb and the positive TC in the current forced through the resistor. The operation of the band-gap cell forces the current in all resistors to be “proportional to absolute temperature” (PTAT). As long as Rb has a TC more positive that the other resistors in the circuit, the voltage across the resistor will have a T
2
term. Thus, the Brokaw curvature correction technique is only a second order (T
2
) correction, whereas real band-gap circuits have a significant amount of higher order curvature. Also, there is no mechanism to easily trim the curvature, once the device is packaged.
Efforts to improve on the Brokaw technique have generally used sophisticated circuits to generate higher order correction terms, often attempting to match the theoretical “TlnT” characteristic of an “ideal” band-gap reference. Two such techniques are disclosed in U.S. Pat. No. 5,352,973 entitled “TEMPERATURE COMPENSATION BANDGAP VOLTAGE REFERENCE AND METHOD” and U.S. Pat. No. 5,519,308 entitled “ZERO-CURVATURE BANDGAP REFERENCE CELL.” These circuits generally require components not available in a low-cost CMOS process, however. Also, as discussed below, real voltage references deviate significantly from the ideal “TlnT” characteristic.
Thus, it would be desirable to have an improved curvature trim technique, suitable for use with CMOS voltage references and providing post-assembly trim.
SUMMARY OF THE INVENTION
The present invention is an apparatus and method for performing curvature trim in a voltage reference circuit that allows a curvature error to be trimmed even after the circuit has been packaged. In one embodiment, the curvature trim is performed by connecting one or more non-linear resistors, such as diffused lightly-doped drain (LDD) resistors, to a band-gap reference. The curvature characteristics of the non-linear resistor is such that the negative curvature error associated with a band-gap reference is cancelled. In fact, this curvature correction is better than that of an ideal “TlnT” corrector. In another embodiment, a set of series non-linear resistors may be selected via selection bits stored in an EEPROM (or other similar non-volatile memory). Since various combinations of the resistors may be selected by programming the EEPROM, the curvature of a band-gap reference can be adjusted after final packaging. This curvature correction method achieves a reliable and accurate correction for the curvature variations that occur with process changes.
In yet another alternative embodiment, one or more resistors associated with the band-gap core may be formed using non-linear resistors, such as diffused LDD resistors. As in the other embodiments, the curvature of the diffused resistors compensates for the normal band-gap curvature, and combinations of resistors may be selected via a programmable non-volatile memory, even after the circuit has been packaged.
Once the voltage reference is packaged, the voltage reference may be calibrated by programming the non-volatile memory. Thus, the present invention provides an improved curvature trim technique, suitable for use with CMOS voltage references and providing post-assembly trim.


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Pease, Robert A

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