Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Phase shift by less than period of input
Reexamination Certificate
1998-11-06
2001-05-01
Le, Dinh T. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Phase shift by less than period of input
C327S295000, C327S259000
Reexamination Certificate
active
06225847
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to complementary clock generators and methods for generating complementary clocks, and more particularly the present invention relates to a CMOS complementary clock generator and a method for generating complementary clocks in which a crossing point less sensitive to variations in process, temperature and supply voltage is provided.
BACKGROUND OF THE INVENTION
In many digital electronic circuits, complementary clock signals having a mutually inverse relationship are required. Because the operating speed of the electronic circuits gradually increases, clock signals having an exactly inverse relation in the time axis are required.
As illustrated in
FIG. 1A
, a conventional CMOS complementary clock generator for generating complementary clocks includes: a same-phase path having two serially connected CMOS inverters Inv
1
and Inv
2
for outputting a clock signal with a phase the same as that of an input clock; and an opposite-phase path having three serially-connected CMOS inverters Inv
3
, Inv
4
and Inv
5
for outputting a clock signal with a phase opposite to that of the input clock. The same-phase path is formed by serially connecting an even number of inverters, while the opposite-phase path is formed by serially connecting an odd number of inverters.
As illustrated in
FIG. 1B
, each of CMOS inverters Inv
1
, Inv
2
, Inv
3
, Inv
4
and Inv
5
is constituted such that PMOS transistor MP
1
and NMOS transistor MN
1
are serially connected, with the gates of PMOS transistor MP
1
and NMOS transistor MN
1
connected to receive an input signal, and an output is outputted through a connection point of the sources and drains of the transistors as illustrated.
This circuit operates in the following manner. For example, if input clock signal Clkin has pulses with a duty cycle of 50%, same-phase output clock signal Clk, with pulses having passed through the same-phase path, i.e., inverters Inv
1
and Inv
2
, have the same phase as that of the input clock, while opposite-phase output clock signal /Clk, with pulses having passed through the opposite-phase path, i.e., inverters Inv
3
, Inv
4
and Inv
5
, have a phase opposite to that of the input clock. Therefore, the clocks have a duty cycle of 50%, and they cross each other at a point of 50%.
If precise complementary clocks having opposite phases at the same timing point are to be formed, the delay of the same-phase path and the opposite-phase path has to be the same, and the number of the inverters of the opposite-phase path has to be larger than that of the inverters of the same-phase path by one. Therefore, the size of the inverters of the opposite-phase path is made to be larger than that of the inverters of the same-phase path, so that the delay of each of the inverters of the opposite-phase path would be smaller than the delay of each of the inverters of the same-phase path. Thus the total delay required in passing through the opposite-phase path is made to be same as the total delay required in passing through the same-phase path.
Generally, the loads of clock signals Clk and /Clk are the same, and the inverters of the opposite-phase path are designed to be bigger than the inverters of the same-phase path. Due to instability of the manufacturing process, the actual sizes of the CMOS inverters are not exactly formed as designed, but instead deviate from the intended design. Therefore, the ratios of the channel widths to the channel lengths of the transistors, i.e., W/L ratios, become different from the intended design. Further, the delay varies in accordance with variations of operating temperature, and, therefore, even if the two paths are matched in the normal operation, the delay can become different if the operating conditions are even slightly different.
As a result, viewed from the time axis, the two complementary clocks are not exactly of an opposite relation, but instead one of them lags behind the other, thereby forming a varying wave pattern. This phenomenon occurs frequently. Further, under certain operating conditions, after maintaining an exactly opposite relationship, if the operating conditions vary even slightly, then a deviating wave pattern is produced.
The basic cause for this phenomenon is as follows. The circuit elements forming the two paths of the same and opposite phases are asymmetrically provided. That is, in the case of the same-phase path, two (or an even number of) inverters form the signal transfer path, while in the case of the opposite-phase path, three (or an odd number of) inverters form the signal transfer path. That is the two paths pass through different kinds of transistors or different numbers of transistors.
SUMMARY OF THE INVENTION
The present invention is intended to overcome the above-described disadvantages of the conventional technique.
Therefore it is an object of the present invention to provide a complementary clock generator and a method for generating complementary clocks, in which complementary clocks of exactly opposite phases can be obtained viewed from the time axis.
In the present invention, the complementary clock signals of more exactly opposite phases with more exact timing may be obtained by providing that the same-phase path and the opposite-phase path are composed of the same kinds and same numbers of circuit elements, and thus when the signals pass through the two paths, the delays are made to be more precisely the same.
In achieving the above object, a complementary clock generator according to the present invention includes: a first inverter for outputting inverted clock signals by inverting input clock signals; a first transmitting switch having an input terminal, an output terminal, a first control input terminal and a second control input terminal, for connecting the input terminal to the output terminal when the input clock signal reaches the first control input terminal, and when the inverted clock signal of the first inverter reaches the second control input terminal; and a second transmitting switch having an input terminal, an output terminal, a first control input terminal and a second control input terminal, for connecting the input terminal to the output terminal when the inverted clock signal of the first inverter reaches the first control input terminal, and when the input clock signal reaches the second control input terminal, whereby same-phase clock signals may be obtained from the output terminal of the first transmitting switch, and opposite-phase clock signals may be obtained from the output terminal of the second transmitting switch.
In order to obtain a sufficient voltage for driving the load, a second inverter is connected to the output terminal of the first transmitting switch, and a third inverter is connected to the output terminal of the second transmitting switch.
Each of the first and second transmitting switches may include: a first PMOS transistor, a first NMOS transistor, a second PMOS transistor, and a second NMOS transistor connected in series; drains of the first PMOS transistor and the second NMOS transistor being connected together so as to serve as an output terminal; gates of the first NMOS transistor and the second PMOS transistor being connected together so as to serve as the first control input terminal; sources of the first NMOS transistor and the second PMOS transistor being connected together so as to serve as the input terminal; and gates of the first PMOS transistor and the second NMOS transistor being connected together so as to serve as the second control input terminal.
In another aspect of the present invention, a method for generating complementary clocks such as same-phase clock signal signals and opposite-phase clock signals from an input clock signal according to the present invention, includes the steps of: inverting an input clock signal to form an inverted clock signal, and supplying input clock signals to two paths which allow signal transmissions at a moment when the input clock signal and the inverted clock signal are simultaneously supplied, so as to m
Le Dinh T.
LG Semicon Co. Ltd.
Loudermilk & Associates
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