Sample-and-hold device

Details Sample-and-hold device Sample-and-hold device

2000-08-04

2001-09-04

Tran, Toan (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific signal discriminating without subsequent control

By amplitude

C327S095000

Reexamination Certificate

active

06285220

ABSTRACT:

BACKGROUND OF THE INVENTION
The invention relates to a sample-and-hold device. It can be applied especially to sample-and-hold devices used upline to an analog-digital converter.
Acquisition systems are generally constituted by an analog chain, an analog-digital conversion and a digital processing chain. The present development of technology is tending to shift the boundary line between digital techniques and analog techniques further upline to the acquisition chain so as to achieve the maximum reduction of the analog part. This trend is aimed especially at simplifying the hardware architecture of systems by carrying out most of the functions, for example the filtering or modulation functions, with digital techniques while at the same time also reducing manufacturing costs.
A major consequence of this development is the great increase in the number of constraints transferred to the analog-digital conversion part since the converter is then at the head, or almost at the head, of the acquisition chain. These constraints can be illustrated by considering the case of a microwave receiver. In this case, the conventional structures have frequency transposition functions. In other words, the received signal undergoes one or more frequency changes before being digitally encoded and demodulated, the encoding and demodulating being then done at low frequency. The systems of the new generation must enable direct encoding of the received signal, namely analog-digital conversion, after only one first frequency change or even directly on the carrier. The analog-digital conversion then has to be done on high frequency or very high frequency signals. It may be noted, by way of an example, that the requirements for these systems, as regards analog-digital converters, are 10 to 14 bits for resolution and linearity, 70 MHz to 900 MHz for input frequencies and one million samples per second to some billions of samples per second for the conversion frequencies.
A key feature of these systems therefore is the analog-digital converter itself. Its performance especially is determined greatly by the quality of sampling which it has at the head of its structure, namely as a function of the sample-and-hold operation.
The function of a sample-and-hold device especially is to receive an analog signal at input that can vary continuously and give a signal known as a sampled signal at output, this being a signal that varies practically by steps. The level of a step is the level possessed by the input signal at the start of the corresponding sampling period, this level being updated at each new sampling period.
A sample-and-hold device works in two phases at each sampling period. During a short phase known as a sampling phase, the output voltage follows the progress of the input voltage. During a holding phase, the output voltage is held at the value that it had before the end of the sampling phase, in spite of the variations in the input voltage.
The qualities expected of a sample-and-hold device include especially the precision with which the input voltage is followed during the sampling phase as well as the holding quality during the holding phase. The output voltage has to faithfully reproduce the variations of the input voltage. With regard to the holding, the output voltage should not vary from the time when the holding phase has begun. Especially, it is desirable to minimize the influence of the parasitic capacitances which tend to cause variations in the output voltage when the input voltage undergoes fast variations.
Another quality expected of the sample-and-hold device is its ability to work at high frequency, especially so that it can sample the signals having a wide frequency spectrum. These qualities are particularly important to make it possible to meet the conversion requirements as cited here above. Another required quality is the ability to work at low power supply voltage, for example 5 volts or 3.3 volts or even less. Indeed, for reasons of energy saving, present-day circuits tend to work at increasingly low voltages.
It is an aim of the invention to provide for the making of a sample-and-hold device that has the best possible qualities with regard to the above criteria and, at the same time, has the simplest possible design and structure in order to minimize space requirement and therefore the cost of the circuit.
SUMMARY OF THE INVENTION
To this end, an object of the invention is a sample-and-hold device comprising a sampling transistor and a sampling capacitor, the sampling transistor being off in hold mode in order to prevent the discharging of the sampling capacitor and conductive in sampling mode to apply a voltage to the capacitor that is substantially equal to the voltage at its base wherein, in order to apply a cut-off voltage to said base, in off mode, that is equal to the voltage present at the sampling capacitor, there is provided a circuit comprising, in series, between two power supply terminals, two MOS type transistors having drain-source channels substantially with the same width-to-length ratio, a bipolar transistor having its base connected to the junction point of the two MOS transistors and its emitter connected to the base of the sampling transistor, a diode biased by a constant current, connected between the source and the gate of one of the two MOS transistors, the gate of the other transistor being connected to the sampling capacitor.


REFERENCES:
patent: 4866301 (1989-09-01), Smith
patent: 5457418 (1995-10-01), Chang
patent: 5471210 (1995-11-01), Wingender et al.
patent: 6031398 (2000-02-01), Karanicolas
patent: 60-160099 (1985-08-01), None
patent: 9-091988 (1997-04-01), None

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