Nonvolatile semiconductor memory device having verify function

Details Nonvolatile semiconductor memory device having verify function Nonvolatile semiconductor memory device having verify function

1999-11-30

2001-05-29

Le, Vu A. (Department: 2824)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185010, C365S185110

Reexamination Certificate

active

06240018

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a non-volatile semiconductor memory device having a rewrite data setting function (i.e. a verify function), and more particularly to a sense amplifier type circuit used for write and read operations.
2. Description of the Related Art
Since a non-volatile semiconductor memory device has an advantage in which data is not lost even if power is turned off, a demand for such non-volatile semiconductor memories has recently increased more and more. Unlike a two-transistor byte-type non-volatile semiconductor memory device, a flash memory or an electrically butch-erasable non-volatile semiconductor memory device may have a memory cell constituted by a single transistor. As a result, the size of the memory cell can be decreased, and it is expected to substitute the flash memory for a large-capacity magnetic disk.
In this type of non-volatile semiconductor memory device, a memory cell array is constituted by arranging memory cells comprising MOS transistors with floating gates in a matrix. A threshold value of the MOS transistor is varied by accumulating a charge in the floating gate, and data is stored by the threshold value. At the time of data write or data read, an electric current is let to flow to the gate insulative film to control data. Thus, a write time varies greatly, depending on a change in process or use condition. This is a principal difference between the above non-volatile semiconductor memory device and a DRAM or SRAM. As a result, a single chip may comprise cells with a short write time and cells with a long write time.
In order to describe the above problems in detail, a conventional non-volatile semiconductor memory device with reference to a NAND type flash memory.
FIG. 1
is a circuit diagram showing a cell structure of the NAND type flash memory. Non-volatile memory cells M
1
to M
16
, each comprising a MOS transistor having a floating gate, are connected in series. The memory cell M
1
at one end of the group of the memory cells M
1
to M
16
is connected to a bit line BL via a selector transistor Q
1
, and the memory cell M
16
at the other end thereof is connected to a common source line S via a selector transistor Q
2
. Each transistor constituting each cell is formed on a single well substrate W. Control gates of memory cells M
1
to M
16
are connected to word lines WL
1
to WL
16
, a control electrode of the selector transistor Q
1
is connected to a selector line SL
1
, and a control gate of the selector transistor Q
2
is connected to a selector line SL
2
.
Each of the memory cells M
1
to M
16
has a threshold value corresponding to data to be stored. When “0” data is stored, the threshold value is set at more than 0 V and less than 5 V. When “1” data is stored, the threshold value is set at less than 0 V. (More appropriately, these threshold values are set in narrow ranges in order to provide some margin.)
FIG. 2
is a graph illustrating a threshold distribution of an N-number of memory cells having threshold values corresponding to the above data “0” and “1”. In the case of a NAND type flash memory, the state in which “1” data is stored is normally called “erase state”, and the state in which “0” data is stored is called “write state”. An operation of shifting the threshold value of a memory cell storing “1” data in a positive direction so that the memory cell may store “0” data is called is “write operation”. An operation of shifting the threshold value (Vth) of a memory cell storing “0” data in a negative direction so that the memory cell may store “1” data is called “erase operation”. This definition of operations may differ in the case of NOR type memory devices.
FIG. 3
is a table showing voltages to be applied to the memory cells at the time of erase and write operations. In the read operation, the bit line BL is precharged at 5 V in a floating state. Then, 5 V is applied to the selector line SL
1
, 0 V is applied to the work line WL of the selected memory cell, 5 V is applied to the word lines WL of the non-selected memory cells. 5 V is applied to the selector line SL
2
, 0 V is applied to the well substrate W, and 0 V is applied to the common source line S. Thus, the transistors of all non-selected memory cells, other than the selected memory cell, are turned on. When “0” data is stored in the selected memory cell, this memory cell is in the non-conductive state and the bit line potential remains at 5 V. If “1” data is stored in the selected memory cell, this memory cell is in the conductive state and the bit line potential is discharged and dropped. A data sense operation is effected by sensing the bit line potential at the time of read-out.
FIGS. 4
,
5
A and
5
B show distributions of thresholds of memory cells at the time of erase and write operations. In the erase operation, the bit line BL is opened, 0 V is applied to the selector line SL
1
, 0 V is applied to the word line WL of the memory cell, 0 V is applied to the selector line SL
2
, 18 V is applied to the well substrate W, and 18 V is applied to the common source line S. Thus, a tunnel current flows across the floating gate and the well via the gate insulative film, and the threshold value lowers to 0 V or less.
FIG. 4
shows a shift of the threshold value distribution.
At the time of the write operation, different voltages are applied in accordance with write data. Specifically, in the case of “0” data write (i.e. in the case of shifting the threshold value), 0 V is applied to the bit line BL. In the case of “1” data write (i.e. in the case of not shifting the threshold value), 9 V is applied to the bit line BL. A potential of 11 V is applied to the selector line SL
1
, 18 V is applied to the word line WL of the selected memory cell, 9 V is applied to the word line WL of the non-selected memory cell, 0 V is applied to the selector line SL
2
, 0 V is applied to the well W, and 0 V is applied to the common source line S. As a result, the selector transistor Q
1
and all memory cells M
1
to M
16
are turned on and set at the same potential as the bit line potential (no consideration is given to a drop in threshold value of transistors). Accordingly, in the memory cell in which 0 V is applied to the bit line BL, a high voltage of 18 V is applied between the channel and the control electrode, a tunnel current flows, and the threshold value shifts to the positive side. On the other hand, in the memory cell in which 9 V is applied to the bit line BL, only 9 V is applied between the channel and the control electrode. Thus, the threshold value is not shifted to the positive side. This “9 V” is called “write prohibition voltage”.
FIGS. 5A and 5B
illustrate the shift of distribution of these threshold values.
As stated above, in the non-volatile semiconductor device, a write operation is effected by using purely physical means of a tunnel current (Fowler-Nordheim tunneling). Thus, the write speed varies from memory cell to memory cell. Even if the same write time is set, a threshold value of a certain memory cell may fall within a range of 0 V to 5 V, but a threshold value of another memory cell may exceed 5 V. This phenomenon is illustrated in FIG.
6
.
Specifically, “0” data is written in a cell with low write speed at time t
1
. However, when “0” data is written in a cell with high write speed, the threshold voltage has exceeded 5 V which is an upper limit value. As described above, at the time of read-out of the NAND type flash memory, 5 V is applied to the word line of the non-selected memory cell to turn on the word line. If the threshold of a certain memory cell exceeds 5 V, data in all memory cells connected in series to this memory cell cannot be read out because the series current path is cut off.
It is therefore necessary to narrow the distribution of thresholds to a predetermined value range. In order to keep a sufficient read-out margin, it is desirable to narrow this distribution to a smaller range.
A bit-by bit verify method has been proposed to solve this problem. According to this m

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