Data processing: structural design – modeling – simulation – and em – Simulating electronic device or electrical system – Circuit simulation
Reexamination Certificate
1999-06-09
2001-04-17
Teska, Kevin J. (Department: 2123)
Data processing: structural design, modeling, simulation, and em
Simulating electronic device or electrical system
Circuit simulation
C703S001000, C703S002000, C703S004000, C716S030000, C716S030000
Reexamination Certificate
active
06219631
ABSTRACT:
FIELD OF THE INVENTION
The present invention generally relates to electronic design automation (EDA) software for semiconductor integrated circuit design and in particular, to a method of generating R,C parameters corresponding to statistically worst case interconnect delays for computer simulation of integrated circuit designs.
BACKGROUND OF THE INVENTION
In deep sub-micron semiconductor process technologies, interconnect delays can easily dominate gate propagation delays as major contributors to the total delay through signal paths of an integrated circuit device. Accordingly, it is important that interconnect delays, and in particular their associated resistance and capacitance (“R,C”) parameters, be thoroughly and accurately accounted for in computer simulations of integrated circuit designs. Otherwise, unexpected timing problems in the resulting silicon may require time consuming and costly redesigns with little or no guidance on how to correct the problems.
One problem in accurately taking into account the effect of interconnect delays, however, is that interconnect material and geometry parameters are subject to significant process-induced variation. Although empirical data gathered from wafer samples fabricated in a given process provide distribution data for such process-induced variation, the determination of statistically worst case (i.e., “3-sigma” or “3-&sgr;”) interconnect delays from such data is not straight-forward. Traditional skew-corner worst case analyses are computationally simple, but prove overly conservative.
One method different than such traditional skew-corner approach for obtaining statistically-based worst case delay and crosstalk for a critical net is described in “3-sigma Worst-Case Calculation of Delay and Crosstalk for Critical Net,” by Norman Chang, Valery Kanevsky, Bill Queen, O. Sam Nakagawa, and Soo-Young Oh, presented at the 1997 ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems in Austin, Tex., on Dec. 4-5, 1997.
One problem with this method, however, is that it only provides worst case delay information for a critical net, and provides no useful information for other nets in the integrated circuit design. Another problem is that the obtained delay information is not applicable to other integrated circuit designs, or even the same integrated circuit design if a subsequent re-layout of the integrated circuit design results in the given net changing its length or route due to re-placement and/or re-routing of the integrated circuit design. Yet another problem is that this method is very slow since it employs extensive use of time consuming Monte Carlo circuit simulations via SPICE. Consequently, such method is generally inadequate for electronic design automation (“EDA”) purposes.
OBJECTS AND SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide a method of generating R,C parameters corresponding to statistically worst case interconnect delays for computer simulation of integrated circuit designs.
Another object is to provide a method of generating R,C parameters corresponding to statistically worst case interconnect delays for computer simulation of integrated circuit designs such that the R,C parameters are of unit length so as to be independent of a given net or integrated circuit design.
Yet another object is to provide a method of generating R,C parameters corresponding to statistically worst case interconnect delays for computer simulation of integrated circuit designs such that the R,C parameters are functions of different interconnect arrangements, and ranges of interconnect widths and thicknesses.
Still another object is to provide an efficient method of generating R,C parameters corresponding to statistically worst case interconnect delays for computer simulation of integrated circuit designs so as to minimize computer processing time to generate such R,C parameters.
These and additional objects are accomplished by the various aspects of the present invention, wherein briefly stated, one aspect is a method of generating R,C parameters corresponding to statistically worst case interconnect delays for computer simulation of integrated circuit designs, comprising the steps of: (a) computing a statistically worst case interconnect delay from randomly generated material and geometry values characterizing an integrated circuit interconnect process; (b) computing a representative set of material and geometry values corresponding to the statistically worst case interconnect delay; and (c) computing R,C parameters corresponding to the statistically worst case interconnect delay from the representative set of material and geometry values.
Additional objects, features and advantages of the various aspects of the present invention will become apparent from the following description of its preferred embodiments, which description should be taken in conjunction with the accompanying drawings.
REFERENCES:
patent: 5301118 (1994-04-01), Heck et al.
patent: 5901063 (1999-05-01), Chang et al.
patent: 6018623 (2000-01-01), Chang et al.
Nakagawa et al, “Circuit Impact and Skew-Corner Analysis of Stochastic Process Variation in Global Interconnect”, IEEE International Conference on Interconnect Technology, pp. 230-232, May 1999.*
Sylvester et al, “Modeling the Impact of Back-End Process Variation on Circuit Performance”, IEEE International Symposium on VLSI Technology, Systems, and Applications, pp. 58-61, Jun. 1999.*
Lugli, “The Monte Carlo Method for Semiconductor Device and Process Modeling”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, pp. 1164-1176, Nov. 1990.
Jung Won-Young
Oh Soo-Young
Broda Samuel
Ingenuus Corporation
Okumoto Victor
Teska Kevin J.
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