Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Slope control of leading or trailing edge of rectangular or...
Reexamination Certificate
1999-07-28
2001-07-03
Nuton, My-Trang (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Slope control of leading or trailing edge of rectangular or...
C327S333000
Reexamination Certificate
active
06255874
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to control and calibration circuitry and in particular to circuitry for adjusting the effective channel width and slew rate of a multi-fingered transistor array.
DESCRIPTION OF RELATED ART
Driver circuits for transmitting data over transmission lines frequently use one or more transistors fingers as the basic driving element. As data rates increase dramatically, new types of driver circuits are required which must comply with rigid interface specifications. One such specification is the Gunning Transceiver Logic specification, commonly referred to as the GTL specification. There are variants of the GTL specification such as GTLP (or GTL+) for Gunning Tranceiver Logic Plus and AGTLP for Advanced Gunning Tranceiver Logic Plus. The GTL, GTLP and AGTLP specifications generally relate to the transmission of data between packaged integrated circuits located on a common mother board at data rates of the order of 66 MHz to 200 MHz, with a typical transmission distance being 1 to 6 inches.
The AGTLP driver includes an N-type transistor having a source connected to circuit common (V
SS
) and a drain connected to the transmission line to be driven. There is some form of pull-up resistance connected to the transmission line located between the driver integrated circuit. Since the AGTLP bus may be bidirectional, both integrated circuits may have individual I/Os containing both drivers and receivers. External pull-up resistors, also known as termination resistors, are tied between the bus and a positive voltage V
TT
. Thus, the driver output is pulled up to a positive voltage (V
TT
) when the N-type transistor is off. The AGTLP interface specification specifies that there is a both a minimum and a maximum value of the large signal output resistance R
ONL
of the N-type transistor when the driver output is low. R
ONL
is specified to have a minimum value of 6.25 &OHgr; and a maximum value of 16.67 &OHgr;. In alternative products, the specification is defined in terms of a current range. For example, the current I
OL
may be specified with a minimum value of 36 mA and a maximum value of 48 mA based on a fixed value of V
OL
equal to +0.6 volts.
A typical integrated circuit will have a large number of driver circuits, each of which must operate within the R
ONL
or I
OL
specification over temperature voltage and process. Since the drain-source voltage must be small, usually no more than 0.6 volts, the transistor must be operated in the linear region where R
ONL
is largely dictated by the transistor size rather the gate-source voltage. Further, in low voltage applications, there is a limitation on the voltage range over which the gate-source voltage may be varied in order to achieve the desired control over R
ONL
or I
OL
.
In addition to the above, the AGTLP specification places limitations on the slew rate of the output of the driver circuit. The falling and rising edges of the output signal must have a slew rate which has a minimum value of 0.3 volts
anosecond and a maximum value of 0.8 volts
anosecond based upon a fixed reference load model.
The present invention permits compliance with specifications, such as the AGTLP specification, over temperature, voltage and process. Further, operation in low voltage applications is achieved. These and other advantages of the present invention will be apparent to those skilled in the art upon a reading of the following Detailed Description of the Invention.
REFERENCES:
patent: 5969554 (1999-10-01), Chan et al.
patent: 6066971 (2000-05-01), Pappert et al.
patent: 6069509 (2000-05-01), Labram
patent: 6081134 (2000-06-01), Labram
patent: 6144240 (2000-11-01), MacQuigg
“Theory and Design of CMOS HSTL I/O Pads”, by G.L. Esch et al.The Hewlett-Packard Journal, Article 5, pp. 46-52, 1998.
Girard & Equitz, LLP.
National Semiconductor Corporation
Nuton My-Trang
LandOfFree
Transistor channel width and slew rate correction circuit... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Transistor channel width and slew rate correction circuit..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Transistor channel width and slew rate correction circuit... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2518065