Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified configuration
Reexamination Certificate
1998-01-30
2001-04-24
Lee, Eddie C. (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified configuration
C257S763000, C257S768000, C257S773000, C257S412000, C257S347000
Reexamination Certificate
active
06222273
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention is directed generally to a via containing a spacer and a method of making the via, and, more particularly, to a via containing a conductive spacer.
2. Description of the Background
It is well known in the semiconductor art to use interconnect structures, known as vias and contacts, to connect an upper conductor of current, such as metal or polysilicon, through a dielectric layer to a lower conductor of current. A via is an electrical connection between two metal layers, and a contact, in contrast, is an electrical connection between anything other than two metal layers, such as between metal and silicon. Vias and contacts are used extensively in very large scale integrated (“VLSI”) circuits, and an average VLSI circuit may contain 16 million vias and contacts.
Vias and contacts are formed by an opening in a dielectric layer and a conductor within the opening. Directional deposition methods, such as evaporation and sputtering, are often used to deposit the conductor within the opening. Such methods, however, often provide poor step coverage and only a thin conductive layer on the vertical wall of the opening. Thin layers are often not sufficient to provide good electrical contact between the upper and lower conductors, and result in a high resistance and a propensity for electromigration failures. Although non-directional deposition methods, such as chemical vapor deposition, provide good coverage of vertical walls, those methods do not provide satisfactory results with conductors which are preferably used in vias and contacts, such as aluminum.
It is well known that step coverage can be greatly improved in directional deposition methods by tapering the wall of a via or contact, so that the wall is not substantially vertical and the diameter at the top is greater than the diameter at the bottom.
One approach to taper a wall is by sputtering or etching the walls of the opening, as disclosed, for example, in U.S. Pat. No. 5,269,880, issued to Jolly et al. That approach, however, often requires additional process steps to provide the bottom of the opening with a protective layer prior to sputtering or etching, and then removing the protective layer following sputtering or etching, as disclosed in the Jolly et al patent.
An alternative approach is to taper the walls by providing a spacer within the via or contact, without disturbing the dielectric layer and without the need for a protective layer to protect the bottom of the opening. An example of such a method is disclosed in U.S. Pat. No. 4,489,481, issued to Jones. Spacers are typically used in critical geometries where dimensions, such as the size of the opening, must be precisely controlled.
Dielectric materials have traditionally been used as spacers, as disclosed in the Jones patent. Oxides, for example, have a smooth surface which allows more precise control of their dimensions. Metals, in contrast, have a “grainy” structure which results in a rough surface. The rough surface, in turn, makes it difficult to precisely control the dimensions of a metal structure. As a result, it was believed that metals were not suited for use in critical geometries, such as spacers, and so the use of metal as a spacer has generally been ignored.
In addition, vias and contacts are typically formed in oxide layers, and while oxide spacers adhere very well to the oxide layer, many metals do not, and thus require an intermediate “glue” layer, such as polysilicon, which adheres well to both oxide and the metal.
Spacers made of a dielectric, however, have the undesirable property of being an insulator. As a result, the use of a dielectric spacer narrows the contact area between the conductor in a via or contact and the upper or lower conductor, resulting in increased resistance. Furthermore, when a dielectric spacer is etched, it leaves dielectric material in the bottom of the opening, which further increases the resistance of the via or contact, or alternatively, requires additional process steps to remove the dielectric material.
Those problems are exaggerated as the density of integrated circuits increases and the size of openings decreases. As the diameter of an opening approaches one micron, the aspect ratio approaches 1 to 1, and directional deposition methods, even when used in conjunction with tapered sidewalls or dielectric spacers, do not provide a reliable electric contact. In those situations, to reliably obtain good electrical contact the opening is usually completely filled with a conductor, known as a “plug”. Plugs, however, are time consuming to produce, and they require several additional process steps. Furthermore, shadowing effects during the formation of plugs often limit their effectiveness as a good electrical connection. As a result, the use of plugs is not always a desirable option.
U.S. Pat. No. 4,507,853, issued to McDavid, discloses the use of metal spacers in a contact between a metal layer and a silicon substrate. There is no disclosure in the McDavid patent, however, of a method of forming a metal spacer in a via. The method disclosed in the McDavid patent does not address the problems present in forming a metal spacer in a via. For example, one problem with forming a metal spacer in a via, which is not addressed in the McDavid patent, is determining when to stop the etch process used to form a spacer from a metal layer deposited in an opening. In the process disclosed in the McDavid patent, a silicon substrate acts as an etchstop. When forming a metal spacer in a via, however, a process that etches the metal layer used to form the spacer will also etch an underlying metal layer. The etch process, therefore, must be stopped before it reaches the underlying metal layer. In an extreme case, the etch process can destroy the underlying metal layer. In a less extreme case, the surface of the underlying metal layer will be recessed by the etch process, increasing both the effective depth and the aspect ratio of the opening, making it more difficult for a subsequent metal layer to make contact with the underlying metal layer. In contrast, if the etch process is stopped too soon, the removal of the conductive layer will not be effective, and a thin film of conductor will remain where it is not wanted.
Thus, the need exists for via spacer with improved electromigration properties, with improved metal step coverage, and with reduced resistance, thereby allowing the use of smaller vias and more dense semiconductor devices.
SUMMARY OF THE INVENTION
The present invention is directed generally to a via spacer and a method of making the same. The via spacer is formed within an opening in a dielectric layer between a first and a second metal layer. The invention includes the step of depositing a spacer layer within the opening of the via so that the spacer layer is in contact with the first metal layer. The invention also includes the step of removing a portion of the spacer layer to leave a spacer within the opening, with a portion of the spacer covering the first metal layer. The second metal layer is deposited over the spacer to complete the connection between the first and second metal layers.
The spacer preferably comprises a material selected from the group comprising refractory metal silicides or their associated nitrides, such as, for example, titanium silicide, titanium nitride, and cobalt silicide. The spacer is preferably tapered and the via may include a glue layer to improve the adherence of the spacer to the dielectric layer.
The invention solves the above-mentioned shortcomings in the prior art by providing a method of forming a conductive spacer, which provides for good step coverage and which does not decrease the contact area of the via.
REFERENCES:
patent: 4489481 (1984-12-01), Jones
patent: 4507853 (1985-04-01), McDavid
patent: 4720908 (1988-01-01), Wills
patent: 4792842 (1988-12-01), Honma et al.
patent: 4977106 (1990-12-01), Smith
patent: 5203957 (1993-04-01), Yoo et al.
patent: 5243220 (1993-09-01), Shibata et al.
patent: 5244534 (19
Blalock Guy
Gonzalez Fernando
Fenty Jesse A.
Kirkpatrick & Lockhart LLP
Lee Eddie C.
Micro)n Technology, Inc.
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