Dividing circuit and transistor stage therefor

Details Dividing circuit and transistor stage therefor Dividing circuit and transistor stage therefor

1998-12-23

2001-03-27

Nuton, My-Trang (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Frequency or repetition rate conversion or control

C327S156000

Reexamination Certificate

active

06208179

ABSTRACT:

TECHNICAL FIELD
This invention relates to a divider circuit, particularly but not exclusively for dividing by odd integers, and to a transistor stage therefor.
BACKGROUND OF THE INVENTION
Clock divider circuits are useful in a number of applications, particularly in counters, where a complete cycle of an output signal represents a predetermined number of incoming clock cycles. The cycles of the output signal can be used to “count” the incoming clock cycles.
It is desirable for such clock divider circuits to work at low power and at high frequencies. For example, desired operating parameters might be a current consumption of 10 &mgr;A at a supply voltage of 3.3 V, with an operating frequency of around 100 MHz. It is also desirable that such divider circuits consume a minimum amount of silicon when implemented on an integrated circuit.
Existing counters are generally based on binary counters. As the basic unit for a binary counter is a divide-by-two unit, extra logic is required to implement counts by odd numbers. This extra logic reduces the highest operating frequency obtainable by the counting circuit and also consumes chip area. Moreover, existing binary counters rarely produce an output signal which has a 50% duty cycle.
Signals having a 50% duty cycle are particularly desirable because in such signals, there is the maximum possible time for the rising and falling edges to achieve safe logic levels. This reduces pulse shrinkage and the consequent uncertainties, both in terms of amplitude and timing of the signal. Moreover, some circuits use both the rising and falling edges of a clock signal, so that it provides greater design flexibility to have a timing point midway through a clock cycle.
The present invention provides a dividing circuit which exhibits an improvement in operating frequency with reduced silicon consumption, particularly for dividing by an odd integer, referred to by N herein.
SUMMARY OF THE INVENTION
According to one aspect of the present invention there is provided a transistor stage for a dividing circuit, the stage comprising:
a first pair of transistors of a first conductivity type connected in series between a first voltage level and an output node;
a second pair of transistors of a second conductivity type connected in series between a second voltage level and said output node,
wherein control nodes of a first transistor of each said transistor pair are connected together to provide an input node for the stage, and
control nodes of a second transistor of each said transistor pair are connected in common to provide a clock node for the stage.
Although two “pairs” of transistors are referred to, there is no need for the transistors to be matched, or otherwise be dependent on one another in their operating parameters.
In the described embodiment, the first transistors are directly connected to the respective first and second voltage levels, and the second transistors are directly connected between the first transistors and the output node. This provides a simple transistor configuration which does not consume an excessive amount of silicon in an integrated circuit yet which provides a high frequency, low power operating transistor stage. In an environment where the first voltage level is a power supply voltage for the stage and the second voltage level is ground, the first pair of transistors are PMOS transistors and the second pair of transistors are NMOS transistors.
Another aspect of the present invention provides a dividing circuit comprising a plurality (N) of transistor stages connected in a ring, each stage comprising:
a first pair of transistors of a first conductivity type connected in series between a first voltage level and an output node;
a second pair of transistors of a second conductivity type connected in series between a second voltage level and said output node,
wherein control nodes of a first transistor of each said transistor pair are connected together to provide an input node for the stage, and control nodes of a second transistor of each said transistor pair are connected together to provide a clock node for the stage,
wherein the input node of each stage is connected to the output node of a preceding stage whereby an output signal is generated at each of said output nodes, each cycle of the output signal representing N cycles of a clock signal applied to said clock nodes of the stages, the output signal having a duty cycle that is closer to 50% than a duty cycle of said clock signal.
In the embodiment described herein, N is an odd integer. The circuit is particularly useful as a divide-by-three or divide-by-five circuit, where N is three or five respectively. However, the number of transistor stages can be extended to any number. It is for counting with such small odd integers that the circuit of the present invention represents a considerable improvement over existing binary counters and necessary associated logic.
The dividing circuit described herein can operate at low powers, for example drawing a current of less than 10 &mgr;A at a supply voltage of 3.3 V and can operate up to high frequencies. It is envisaged that operation up to a frequency of 1 GHz is possible, limited only by the characteristics of a single CMOS transistor.
For a better understanding of the present invention and to show how the present invention may be carried into effect, reference will now be made by way of example to the accompanying drawings and detailed description.


REFERENCES:
patent: 3749937 (1973-07-01), Rogers
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patent: 4369379 (1983-01-01), Hull
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patent: 4953187 (1990-08-01), Herold et al.
patent: 4965531 (1990-10-01), Riley
patent: 5425074 (1995-06-01), Wong
patent: 5514990 (1996-05-01), Mukaine et al.
patent: 0 746 109A1 (1996-04-01), None
patent: 62-026920 (1987-04-01), None
patent: WO 90/05413 (1990-05-01), None
Suzuki et al., “Clocked CMOS Calculator Circuitry.”IEEE Journal of Solid-State CircuitsDec. 1973, pp. 462-469.

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