Nonvolatile semiconductor memory

Details Nonvolatile semiconductor memory Nonvolatile semiconductor memory

2000-06-28

2001-09-18

Elms, Richard (Department: 2824)

Static information storage and retrieval

Powering

C365S185170

Reexamination Certificate

active

06292423

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 11-181877, filed Jun. 28, 1999, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
The present invention relates to a nonvolatile semiconductor memory capable of storing data of a plurality of bits in one cell transistor and, more particularly, to an improvement in the data holding characteristics of the cell transistor.
As a general nonvolatile semiconductor memory, an electrically erasable programmable EEPROM, particularly, a flash memory is well known. The flash memories can be categorized into a NAND type and a NOR type memories. The conventional problems will be explained by exemplifying a NAND flash memory.
FIG. 1
is an equivalent circuit diagram showing memory cells of a NAND flash memory.
As shown in
FIG. 1
, the memory cell contains a selection transistor, a plurality of cell transistors (cell transistors
1
to
4
), and a switching transistor that are connected to each other between a bit and a source lines. Each cell transistor has a floating gate. In this specification, the memory cell shown in
FIG. 1
will be called a memory cell string for convenience. Memory cell strings are arranged in a matrix on a memory cell array, as shown in FIG.
2
.
In the NAND flash memory in which one cell transistor stores 1-bit data, logic values “1” and “0” of data stored in the cell transistor correspond to “positive” and “negative” of the threshold voltage of the cell transistor, respectively. Whether the threshold voltage of the cell transistor is “positive” or “negative” is determined in accordance with an electron charge state in the floating gate. When electrons are injected in the floating gate, the threshold voltage is “positive”; and when electrons are discharged from the floating gate, the threshold voltage is “negative”. Electrons are injected/discharged to/from the floating gate via the first gate insulating film between the floating gate and the channel region using the tunnel effect.
In writing data in the cell transistor, the switching transistor is turned “off”.
In reading out data from the cell transistor, the switching transistor is turned “on”. At the same time, the selection transistor connected to a cell transistor (to be referred to as a selected cell transistor) from which data is to be read out is turned “on”. The control gate of the selected cell transistor is set to logic “0” (e.g., ground potential), whereas the control gate of each unselected cell transistor is set to logic “1”. If the threshold voltage of the selected cell transistor is “negative”, and ifs control gate is at logic “0”, the cell transistor is turned “on”; and if the threshold of the selected cell transistor is “positive”, and its control gate is at logic “0”, the cell transistor is turned “off”. In this manner, the data logic is discriminated between “1” and “0” depending on whether the selected cell transistor is “ON” or “OFF”. Since the control gate of each unselected cell transistor is set to logic “1”, the unselected cell transistor is turned “on” regardless of whether the threshold voltage is “positive” or “negative”.
In the NAND flash memory, each unselected cell transistor among series-connected cell transistors is turned “on”. Data stored in a selected cell transistor is read out depending on whether the selected cell transistor is turned “on” or “off”, i.e., a current flows or does not flow through the memory cell string.
When the selection transistor is “not selected”, the control gate of a cell transistor connected to the unselected selection transistor is set to logic “0” to stand by.
To store data of a plurality of bits in one cell transistor in the NAND flash EEPROM, a plurality of threshold voltages are set for the cell transistor. For example, to store 2-bit data in one cell transistor, four threshold voltages are set, as shown in Table 1.
TABLE 1
Threshold
Storage Data
Voltage
D1
D2
Vth1
0
0
Vth2
0
1
Vth3
1
0
Vth4
1
1
Vth1<Vth2<Vth3<Vth4
Letting (D1,D2) be 2-bit memory data, as shown in Table 1, the threshold voltages of the cell transistor correspond to combinations of data (D1,D2), respectively. For example, threshold voltages Vth1, Vth2, Vth3, and Vth4 correspond to combinations (0,0), (0,1), (1,0), and (1,1) of data (D1,D2), respectively. Assuming that the threshold voltages Vth1 to Vth4 have a relation “Vth1<Vth2<Vth3<Vth4”, as shown in Table 1, the threshold voltage Vth1 is set to a negative value, and the threshold voltages Vth2, Vth3, and Vth4 are set to positive values.
Data read from this cell transistor will be explained with reference to FIG.
3
.
When cell transistor
2
shown in
FIG. 1
is selected, a selected word line WL
2
is set to a potential between the threshold voltages Vth1 and Vth2. If the threshold voltages Vth1 and Vth2 have negative and positive values, respectively, the selected word line WL
2
is set to 0V. This potential is “selected word line potential 1”. At this time, the potentials of unselected word lines WL
1
, WL
3
, and WL
4
are set higher than the threshold voltage Vth4 so as to turn on at least one of cell transistors
1
,
3
, and
4
even at the highest threshold voltage Vth4 (unselected word line potential is not shown).
If the threshold voltage of cell transistor
2
is “Vth1”, cell transistor
2
is turned on. As a result, a bit line connected to cell transistor
2
is discharged via the selection transistor, cell transistors
1
to
4
, and switching transistor. This state is detected by a sense amplifier. At this time, D1=“0” and D2=“0” are determined.
If the threshold voltage of cell transistor
2
is “Vth2” or higher, cell transistor
2
is kept off, and the bit line is kept charged.
Then, the selected word line WL
2
is set to a potential between the threshold voltages Vth2 and Vth3. This potential is “selected word line potential 2”. If the threshold voltage of cell transistor
2
is “Vth2”, cell transistor
2
is turned on. The bit line connected to cell transistor
2
is discharged via the selection transistor, cell transistors
1
to
4
, and switching transistor. This state is detected by the sense amplifier. At this time, D1=“0” and D2=“1” are determined.
If the threshold voltage of cell transistor
2
is “Vth3” or higher, cell transistor
2
is kept off, and the bit line is kept charged.
Then, the selected word line WL
2
is set to a potential between the threshold voltages Vth3 and Vth4. This potential is “selected word line potential 3”. If the threshold voltage of cell transistor
2
is “Vth3”, cell transistor
2
is turned on. The bit line connected to cell transistor
2
is discharged via the selection transistor, cell transistors
1
to
4
, and switching transistor. This state is detected by the sense amplifier. At this time, D1=“1” and D2=“0” are determined.
If the threshold voltage of cell transistor
2
is “Vth4” or higher, cell transistor
2
is kept off, and the bit line is kept charged. This state is detected by the sense amplifier. At this time, D1=“1” and D2=“1” are determined. Alternatively, the potential of the selected word line WL
2
may be set to the threshold voltage Vth4 or higher, and the discharge state of the bit line may be detected by the sense amplifier.
Upon completion of data read, the potentials of the word lines WL
1
to WL
4
are set to 0V. The potentials of the word lines of cell transistors which are connected to a selection transistor which is unselected, i.e., receives a signal SG of “0” are also set to 0V.
A memory (to be referred to as a multilevel memory for convenience) in which one cell transistor stores data of a plurality of bits requires a larger number of threshold voltages than a memory (to be referred to as a binary memory for convenience) in which one cell transistor stores 1-bit data. For this reason, the highest threshold voltage in the multilevel memory becomes higher than the highest thresho

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