Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Synchronizing
Reexamination Certificate
1999-06-04
2001-03-06
Ton, My-Trang Nu (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Synchronizing
C327S150000
Reexamination Certificate
active
06198321
ABSTRACT:
FIELD OF THE INVENTION
The invention relates to a device for the generation of a drive signal that is phase-shifted with respect to an external synchronization signal. Further, the invention relates to systems for the processing of horizontal or linear sweeping signals in a monitor.
BACKGROUND OF THE INVENTION
A horizontal synchronization signal received by a monitor has a frequency usually ranging from 15 to 150 KHz. Generating a drive signal that is resynchronized with the monitor and phase-shifted by a precise value with respect to the external synchronization signal, can be a problem. When the device is balanced, the phase shift comprises a fixed value that does not vary from line to line and a dynamic value which may change from line to line. This dynamic value corresponds especially to variations in balance or fringe effects and depends on the characteristics of the monitor. This phase shift is usually processed by an analog device and thus does not make it possible to externally program these values, with the circuits of the monitor, to modify the phase-shift curves. Usually, it is sought to adjust these phase-shift curves as a function of the monitor requirements.
FIG. 1
shows a conventional phase-locked loop including a phase comparator
1
, between the external synchronization signal HSYNC and the reference signal PHI
1
, which delivers a signed error E at its output. In this example, this error E is applied to a digital filter integrator
2
which, in an output register, provides digital information element C comprising an integer part and a fractional part. A digital filter
2
integrator of this kind is described, for example, in patent application EP A 644 654 entitled “First Order Digital Integrator and Filter” which is incorporated by reference herein and may be referred to for a detailed operation of this circuit.
This signal C is applied to a frequency synthesizer
3
that provides a synthesized signal CKGEN at output. This synthesizer makes it possible to carry out the division, by the integer value INT(C) or by the immediately greater integer value INT(C)+1, of the N phases Fi
0
and Fi
15
of a high frequency signal F applied to the synthesizer. This is carried out according to a principle described in the European patent application EP 0 641 083 entitled “Frequency Synthesizer” which is also incorporated by reference herein and may be referred to for a detailed operation of this circuit.
The synthesizer comprises a multiplexer MUX for the generation of the synthesized signal CKGEN. This multiplexer receives N phase signals NF
0
to NF
15
, and outputs the synthesized signal CKGEN. The synthesizer selects the phase, among the N phases Fi
0
to Fi
15
of the high frequency signal F, at which the locking is achieved. This phase selection information PHISELECT controls the multiplexer MUX. In practice, the locking phase may change at each line and therefore the output signal CKGEN has phase leaps. These phase leaps cannot be greater than the difference between two consecutive phases, in the example 325 ps.
This synthesized signal CKGEN is looped to a multiplier
4
, which multiplies the signal by M, to provide the resynchronized reference signal PHI
1
having the same frequency as HSYNC. In the example, it is desired to have the synthesized signal CKGEN at the frequency of 24 MHZ. Starting with a high frequency signal at 192 MHZ, the digital information C is close to 8 (for 8×24 MHZ=192 MHZ). M is then deduced therefrom to find the frequency of the external synchronization signal HSYNC, such that the frequency of the synthesized signal CKGEN is equal to M times the frequency of HSYNC. The output of the multiplier provides the resynchronized signal PHI
1
which, like CKGEN, may have phase leaps. For each line, the corresponding current locking phase is the same as that of the signal CKGEN. It is therefore the one defined by the information PHISELECT.
SUMMARY OF THE INVENTION
Replacing this analog device by a digital device is desired. Phase-locked loop circuits in digital form are already known. Also, it is noted that, in digital mode, the phase shift generally results in a time lag. It is necessary firstly to generate, from an external synchronization signal, a resynchronized reference signal. It is then necessary to compute the phase-shift error between these reference signals and the drive signal in order to be able to correct this drive signal.
The reference signal may be obtained from the prior art digital phase-locked loop represented in FIG.
1
. The high frequency signal F used must be very stable and, in practice, is given by an analog phase-locked loop PLL
0
, for example, as represented in Figure
3
. In the example, this loop PLL
0
makes it possible to provide the N=16 phases Fi
0
to Fi
15
of the high frequency signal F at 192 megahertz (MHZ). These 16 phases are shown in FIG.
5
. The difference between two consecutive phases is then 325 picoseconds (ps). There is thus obtained a pseudo clock signal at very high frequency HF, at 3.2 gigahertz (GHz).
More particularly, it is desired to make the phase-shift correction by a digital circuit capable of working at very high frequency and therefore capable of performing very fine phase-shift corrections. These very fine phase-shift corrections are performed to obtain a resynchronized and phase-shifted drive signal having a value HPOS with a very fine precision, as compared with the external synchronization signal HSYNC. This value HPOS is determined by programming, and it is controlled by circuits of the monitor.
To obtain this precision in the phase shift, the invention uses the high frequency signal F at 192 MHZ, given by the analog phase-locked loop PLL
0
and the reference signal PHI
1
given by the first digital phase-locked loop PLL
1
. However it has been seen that this reference signal PHI
1
has phase leaps. If the phase-shift of the drive signal is measured and corrected on the basis of the reference signal PHIL, it is necessary to take account, at each new line, of the current locking phase in the loop PLL
1
on which this reference signal PHI
1
is resynchronized, to obtain an accurate error measurement. Taking these phase leaps into account results in added time.
Furthermore, it is desired to measure the error to the nearest 325 picoseconds between this reference signal PHIL and the drive signal, in taking account of the programmed value HPOS since it is desired to have a phase shift at equilibrium between this drive signal and the reference signal equal to HPOS. The error signal should be at 325 ps. If a phase comparator is used, it must make it possible to obtain both a resolution and a precision of this kind.
Finally, the measurement of error given by the phase comparator should again be sampled, in order to find out how many cycles of the very high frequency HF signal at 3.25 GHz are contained in the phase shift (number of 325 ps cycles). In sampling this very high frequency, there is necessarily an error amount per edge of the error signal.
One approach to these different technical problems linked to this measurement of error has been found in a device comprising a digital phase-locked loop to servo-control a drive signal with reference to the reference signal PHI
1
and comprising a phase-measurement circuit, a circuit for the digital computation of the phase shift to be performed and a phase-shift circuit. According to the invention, the measurement circuit comprises a first circuit for the rough measurement of the phase shift between the drive signal or a delayed derived signal and the reference signal, controlled by a fixed phase PHIREF of the high frequency signal F, independent of the current locking phase in the loop PLL
1
. The shift between this fixed phase and the current phase is subsequently and digitally accounted for. In this way, the system is no longer hampered by the phase leaps of the signal PHI
1
.
In one embodiment, the rough measurement circuit comprises elements to reposition the reference signal with respect to a fixed phase of the sy
Dubois Nathalie
Ianigro Corrine
Lebouleux Nicolas
Marchand Benoit
Allen Dyer Doppelt Milbrath & Gilchrist, P.A.
Galanthay Theodore E.
Nu Ton My-Trang
STMicroelectronics S.A.
LandOfFree
Device for the generation of a drive signal phase-shifted... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Device for the generation of a drive signal phase-shifted..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Device for the generation of a drive signal phase-shifted... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2513462