Source and drain sensing

Details Source and drain sensing Source and drain sensing

1999-12-30

2001-09-18

Le, Vu A. (Department: 2824)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185180, C365S185210

Reexamination Certificate

active

06292395

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to sensing single and multiple bit non-volatile memories to determine what value is represented. In particular, it relates to a device and method for sensing the source and drain of the cell being read.
2. Description of the Related Art
Sense amplifiers are used to determine the data value or values stored in a non-volatile memory. In a conventional sensing scheme, a current through the memory cell being sensed is compared to a reference current by a current-sensing sense amplifier. The ratio of the desired cell current to the reference current is referred to as the sensing ratio SR. A conventionally preferred sensing ratio is 2:1. When the current through the selected cell is more than twice the reference current (Ir), a value of “1” is sensed. When the current is significantly less than twice the reference current, a value of “0” is sensed. A current close to the sensing ratio may take longer to sense or may produce an indeterminate result. Manufacturing and operating variations limit the effectiveness of current sensing.
Newer, low voltage memory cells and multi-bit memory cells are difficult to sense using the conventional current sensing scheme described above. Low voltage memory cells are designed to minimize current flow. Multi-bit memory cells have less read margin, due to the multiple threshold voltages that define the multiple bit values of a cell. Accordingly, a novel approach that relies on sensing both the source and drain of a selected cell, as an alternative to sensing only the drain, is described below.
SUMMARY OF THE INVENTION
In one embodiment, the present invention provides a device for sensing the threshold voltage of at least one non-volatile memory cell, selectable from an array of memory cells, comprising: at least one non-volatile memory cell; a first voltage generator, coupled to the drain of the memory cell; at least one reference cell, coupled to the source of the memory cell; a second voltage generator, coupled to the reference memory cell; and a differential amplifier coupled to the first and second voltage generators. This embodiment may additionally include a current source having an input stimulus; a current mirror coupled to the current source; a voltage biasing circuit coupled to the current mirror; a virtual ground; and a current limiter coupled between the source of the memory cell and the virtual ground, further coupled and responsive to the voltage biasing circuit. One aspect of this embodiment may be that the gate of the reference cell is coupled and responsive to the first voltage generator. Other aspects may be that the current source is comprised of a miniarray having drain, source and gate nodes, and a particular voltage is applied to the miniarray gate node as the input stimulus, and the miniarray is formed during the same process as the non-volatile memory cell.
Another embodiment provides a device for sensing the threshold voltage of at least one non-volatile memory cell which is selectable from an arranged collection of memory cells and has a drain and source, comprising: a conductor; at least one non-volatile memory cell, coupled to the conductor; a first voltage generator, coupled to the non-volatile memory cell; at least one reference memory cell, coupled to the conductor; a second voltage generator, coupled to the reference memory cell; and a differential amplifier coupled to the first and second voltage generators. As above, this embodiment may additionally include a current source having an input stimulus; a current mirror coupled to the current source; a voltage biasing circuit coupled to the current mirror; a virtual ground; and a current limiter coupled between the source of the memory cell and the virtual ground, further coupled and responsive to the voltage biasing circuit. The aspects of gate coupling, miniarray current source and miniarray formation described above may also be part of this embodiment.
An alternative embodiment of the present invention provides a method of sensing a non-volatile memory cell which is selectable from an arranged collection of memory cells and has a drain and source, comprising the steps of: coupling the non-volatile memory cell to a conductor; coupling a reference memory cell to the conductor; coupling the non-volatile memory cell to a first voltage generator; coupling the reference memory cell to a second voltage generator; and sensing with a differential amplifier the voltages of the first and second voltage generators. This embodiment may further include the step of driving the gate of the reference memory cell from the first cell level voltage generator. An aspect of this embodiment may be that the non-volatile memory cell and the reference memory cell are coupled to the conductor through a current limiter, and the method further includes the step of driving the current limiter device responsive a current source including a miniarray which was formed during the same process as the non-volatile memory cell.
In a further embodiment, the present invention provides a device for sensing multiple threshold voltages of at least one multi-level non-volatile memory cell, which is selectable from an arranged collection of memory cells and has a drain and source, comprising: at least one memory cell, having a source and drain; a first voltage generator, coupled to the drain of the memory cell; at least three reference cells having threshold voltages corresponding to threshold voltages for data values stored in the memory cell, coupled to the source of the memory cell; a second voltage generator, coupled to the drain of reference memory cell; and a differential amplifier coupled to the first and second voltage generators. This embodiment may also include the current source, current mirror, voltage biasing circuit, virtual ground and current limiter summarized above. The aspects of gate coupling, miniarray current source and miniarray formation described above may also be part of this embodiment.
Alternatively, the present invention may be embodied in a device for sensing multiple threshold voltages of at least one multi-level non-volatile memory cell which is selectable from an arranged collection of memory cells and has a drain and source, comprising: a conductor; at least one multi-level non-volatile memory cell, coupled to the conductor; a first voltage generator, coupled to the multi-level non-volatile memory cell; a plurality of reference memory cells, coupled to the conductor; a second voltage generator, coupled to the multi-level non-volatile memory cell; logic for selecting among reference memory cells to be compared to the multi-level non-volatile memory cell; and a differential amplifier coupled to the reference cells and the non-volatile memory cell. It may also include a current source having an input stimulus; a current mirror coupled to the current source; a voltage biasing circuit coupled to the current mirror; and a current limiter coupled between the conductor and both the reference memory cell and the non-volatile memory cell, further coupled and responsive to the voltage biasing circuit. The aspects of miniarray current source and miniarray formation summarized above may also be part of this embodiment.
A multi-level memory cell embodiment employing the concepts of the present invention may provide a method of sensing for a multi-level non-volatile memory, the memory cell having a source and drain and being selectable from an arranged collection of memory cells, by comparing it to first, second and third reference cells having sources and drains, comprising: coupling the drain of the memory cell to a first voltage generator; coupling the drain of the first reference cell having a threshold voltage Vt1 to a second voltage generator; comparing the voltages of the first and second voltage generators using a differential amplifier to produce a first bit value; coupling alternatively the drain of the second reference cell having a threshold voltage Vt0 or the drain of the third reference cell having a thr

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