Flexible DRAM array

Details Flexible DRAM array Flexible DRAM array

1997-12-29

1999-05-11

Nguyen, Tan T.

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

365149, G11C8/00

Patent

active

059035110

ABSTRACT:
A DRAM array comprised of plural wordlines and plural bitlines, bit charge storage capacitors associated with the bitlines and wordlines, cell access field effect transistors (FETs) having their gates connected to the wordlines and their source-drain circuits connected between the bitlines and the charge storage cells, for enabling reading or writing data from or to the charge storage capacitors, and programmable addressing apparatus for causing the wordlines, once addressed, to selectively enable either one or more than one cell access FET, whereby data can be selectively read from or written to one or more than one charge storage capacitor.

REFERENCES:
patent: 5289429 (1994-02-01), Watanabe
patent: 5367655 (1994-11-01), Grossman et al.

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