Static information storage and retrieval – Floating gate – Particular connection
Reexamination Certificate
1999-08-11
2001-07-17
Nguyen, Viet Q. (Department: 2818)
Static information storage and retrieval
Floating gate
Particular connection
C365S185010, C365S185050, C365S185120, C365S185130, C365S185170
Reexamination Certificate
active
06262914
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The technical field of this invention is FLASH memory an particularly programming and clearing FLASH memory.
BACKGROUND OF THE INVENTION
Semiconductor memories of several types have become key support hardware for today's computer systems. While DRAM (dynamic random access memory) has been used mainly in the form of dedicated chips, most of the other types have been employed both as dedicated chips and as embedded memory, located on the main central processing unit chip.
These other types include: (1) SRAM (static random access memory), (2) ROM (read-only memory), (3) EPROM (electrically programmable read-only memory), (4) EEPROM (eraseable electrically programmable read-only memory), and (5) FLASH (an acronym meaning simply “high speed eraseable, electrically programmable read-only memory”). The last three, EPROM, EEPROM, and FLASH use basically similar device technology process steps and device structure at the heart of the memory element. The key device is a dual-gate NMOS transistor. A first gate, called the control gate, is normally connected to the circuit node which electrically drives it. A second gate is floating electrically and is used to hold a charge. This charge can be altered electrically by applying a combination of specific values of impressed voltages on the normal gate and source/drain terminals. The charge present on the floating gate determines whether a logical “0” or a logical “1” is stored at the cell location of the floating gate transistor.
This floating gate structure is a compact device. The precision process from which it is formed provides a transistor well controlled in its characteristics. There are three basic differences of the FLASH structure over the EPROM structure. In the FLASH structure the geometric details around the periphery and within the active area of the gates have been modified to make the device more amenable to programming in-sitsu, that is programming while the device is located in its application socket. The gate oxide thickness has been reduced in the FLASH memory element transistor. This allows for charge tunnelling to occur and makes possible channel erasing. In channel erasing the central active area of the channel participates in the erasing rather than only at the active gate periphery. The FLASH device also includes additional required biasing circuitry to allow erasing.
In order of historical sequence, the PROM was first used for read-only memory applications and the devices were programmed by a masking operation. In order to satisfy the need for custom programming with short turn-around time at the user's location, the EPROM was developed next. Such EPROMs can be erased only by UV light, thus the and packages have to be transparent. This, by its nature, ruled out embedded processor usage, as the embedded processors can not be encased in such packages.
The EEPROM was developed next and it allowed electrical erasing without UV light. The EEPROM required an extra transistor for select in each cell and this made the chip area per cell too costly. The FLASH memory cell surmounts all the objections, giving excellent performance and excellent cell density. The conventional FLASH memory remains the solution of choice in read-only memory applications. The FLASH memory also has seen needed incremental technology improvements, leading to better producibility, reliability, and performance. Ease of programming is also an area undergoing continued investigation and experimentation. Texas Instruments FLASH memory devices differ in two important respects from other FLASH memory devices being produced.
First, some prior art FLASH memories use N-epitaxial structures or even simple P-substrate structures, which do not allow for selective bias to the back-gate of a cell.
FIG. 1
shows such an N-epitaxial structure. Selective bias cannot be applied to the N-epitaxial back-gate which is common to all devices.
FIG. 2
shows the Texas Instruments prior art device structure, a P-substrate epitaxial structure having an N-well back gate. This back gate has several advantages leading to the possibility of generating isolated components for effective circuit use, but most notably, enables a simple “block or sector” pre-programming step which erases either blocks or sectors of the whole array at once. Blocks and sectors are illustrated in FIG.
3
.
FIG. 3
illustrates three common organizations for FLASH memories. In the block configuration all locations are erased at once in a block erase operation. In the boot-block configuration, addressing may be directed to the programming sector or the boot block sector. Therefore, this configuration is suited to sector erase. In the fully sectored configuration, the erasing is carried out individually in multiple sectors. Conventional FLASH memories are committed to more complex erasing on a byte-by-byte basis. Secondly, Texas Instruments arrays use a switched “source select” line, operating to apply a virtual ground only to those bits being programmed or READ.
A typical prior art FLASH memory circuit configuration is shown in FIG.
4
. The memory cell consists of (a) the floating gate N-Channel transistor
401
and (b) associated bit line
402
drive, word line
403
, drive and virtual ground
404
, and switch circuitry
406
.
FIG. 5
illustrates an array of such memory cells. These are normally arranged in groups of either 16 or 32 columns. These groups have a common sense amplifier such as
533
, and either 8 or 16 sense amplifiers
533
,
537
,
538
and
539
form one eight-bit byte or one sixteen-bit word of output data.
During in programming or erasing sense amplifier
533
is used to verify that the correct logical state is stored at the desired location. In application usage for reading, sense amplifier
533
is used to detect the desired data and provide interface from the limited drive strength of the memory cell to a CMOS (or TTL) output buffer to the chip terminals or the embedded function's internal terminals.
FIG. 6
shows eight bits in detail, four least significant bits (LSB) and four significant bits (MSB) of a sixteen or thirty-two bit column group. Two words are shown, word
0
and word N.
The floating gate N-Channel transistor (
401
of
FIG. 4
) has the characteristics illustrated in FIG.
7
. When this transistor has a zero charge on its floating gate, the transistor has the I-V (current-voltage) characteristic of curve “A”. With a negative charge “Q
−
” on the floating gate, the I-V characteristic shifts to curve “B”. With a positive charge “Q
+
” on the floating gate, the I-V characteristic shifts to curve “C”.
Programming consists of addressing a particular word line
403
and a particular bit line
402
. An appropriate voltage higher than the normal operational voltage is impressed on that word line. Simultaneously, the addressed bit line
402
is driven with the voltage required to charge the floating gate to value Q
−
(
FIG. 7
) associated with storing the desired logic “0” level. Similarly, channel erasing by block or sector consists of addressing all appropriate bits simultaneously and impressing an appropriate voltage higher than the normal operational voltage on the back gate line while simultaneously driving the word line to zero volts. This results in a charge Q+ (
FIG. 7
) on the floating gate, thus storing the desired logic “1” level.
Programming and erasing are normally carried out by applying pulses to the word line or the bit line requiring the higher voltage. The appropriate voltages are illustrated in the table of FIG.
8
. By convention, the term “programming” is synonymous with writing “0” and “erasing” is synonymous with writing “1”.
The “READ (normal verification)” operation shown in
FIG. 8
verifies that programming has been successful. If the first group of programming pulses does not yield the desired result, additional pulses (a second pass) may be applied. This frequently will drive the floating gate charge to the desired level. Excessive passes of this type could degrade the dev
Marotta Giulio G.
Santin Giovanni
Smayling Michael C.
Kempler William B.
Nguyen Viet Q.
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
LandOfFree
Flash memory segmentation does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Flash memory segmentation, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Flash memory segmentation will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2509146