Semiconductor device and memory system

Static information storage and retrieval – Floating gate – Multiple values

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Details

36518522, 36518524, G11C16/04

Patent

active

059034955

ABSTRACT:
A semiconductor memory device comprises a memory cell array having electrically erasable and programmable memory cells arranged in rows and columns, each memory cell capable of storing n-value data (n is 3 or a greater natural number), and a data circuit having m latch circuits for holding data items read from said memory cells, wherein data items read from said memory cells and held in k latch circuits (k<m) are output from the memory device before data items read from said memory cells are held in the remaining (m-k) latch circuits, during data-reading operation.

REFERENCES:
patent: 5163021 (1992-11-01), Mehrotra
patent: 5521865 (1996-05-01), Ohuchi
patent: 5602789 (1997-02-01), Endoh
patent: 5677869 (1997-10-01), Fazio

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