Boots – shoes – and leggings
Patent
1996-10-29
1999-05-11
Teska, Kevin J.
Boots, shoes, and leggings
364489, 364490, 364483, G06F17/50
Patent
active
059034769
ABSTRACT:
A system and method for modeling power consumed by a logic cell in a estimation process over an integrated circuit, represented by logic cells and connections between cells, using a three dimensional power modeling table (3-D power table). The 3-D power table utilizes dual output capacitance indices and a single input transition time (which can be a weighted average input transition time) index. Each 3-D power table of the present invention includes a set of index reference points for the first output capacitance index, a set of index reference points for the second output capacitance index, a set of index reference points for the input transition time, and a set of power reference points that correspond to the above index reference points. For a given set of values input for: (1) the first output capacitance index; (2) the second output capacitance index; and (3) the input transition time index, linear interpolation is performed across the three indices to arrive at the given output power consumption value. The 3-D power tables are used to accurately model the power consumed by a cell having two outputs which are functionally equal or opposite, for instance, a flip-flop with Q and Q' outputs. A library developer can specify a 3-D power table having three indices, input transition time, output1 capacitance (e.g., for Q), and output2 capacitance (e.g., for Q'). The power value output is then an accurate measure of the total power consumed by the dual output cell during the output transition.
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Schneider et al., "Fast Power Estimation of Large Circuits", IEEE, 1996, pp. 70-78.
Lin Yueqin
Mauskar Ashutosh S.
Nedelchev Ivailo
Olson Janet
Sproch James
Phan Thai
Synopsys Inc.
Teska Kevin J.
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