Nonvolatile integrated circuit memory devices having...

Details Nonvolatile integrated circuit memory devices having... Nonvolatile integrated circuit memory devices having...

1999-10-28

2001-01-30

Nelms, David (Department: 2818)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185280, C365S185290

Reexamination Certificate

active

06181606

ABSTRACT:

RELATED APPLICATION
This application is related to Korean Application No. 98-46481, filed Oct. 30, 1998, the disclosure of which is hereby incorporated herein by reference.
FIELD OF THE INVENTION
The present invention relates to integrated circuit devices, and more particularly to integrated circuit memory devices and methods of operating integrated circuit memory devices.
BACKGROUND OF THE INVENTION
A flash EEPROM cell transistor typically has a floating gate which is completely surrounded by insulation and generally disposed between its source and drain region formed in a silicon substrate and a control gate coupled to a word line. In this cell, charge carriers (i.e., electrons) can be injected through the insulation to the floating gate when the cell is programmed. Operation of a flash EEPROM device is typically divided into three modes including programming, erasing and reading.
A flash cell is typically programmed by hot electron injection from the substrate to the floating gate. To induce such an effect, it is necessary to supply the control gate and drain of the cell with program volages (e.g., about 8-12 V for the control gate and 5-6 V for the drain) which are higher than read voltages (e.g., 4-5 V for the control gate, about 1 V for the drain, and 0 V for the source and bulk) for reading data out of the cell while grounding its source and bulk.
During the programming mode, the floating gate accumulates the hot electrons and traps the accumulated electrons. The accumulation of a large quantity of trapped electrons on the floating gate causes the effective threshold voltage of the cell transistor to increase (e.g., about 6-7 V). If this increase is sufficiently large, the cell transistor will remain in a non-conductive state when read voltages are applied thereto during a read operation. In this programmed state, the cell may be said to be storing a logic 0 (“OFF cell”). Such a programmed state of the cell remains even when power supply is interrupted.
Erasing a flash cell transistor includes removing charge accumulated on its floating gate. The erasing of a flash cell can be carried out, for example, by applying a negative high voltage (e.g., about −10 V) to its control gate and an appropriate positive voltage (e.g., 5-6 V) to its bulk while floating its source and drain. This causes cold electron tunneling (i.e., Fowler-Nordheim tunneling) through the thin insulation between the floating gate and the bulk, leading to a decrease in the threshold voltage of the cell transistor (e.g., 1-3 V). The erase voltages may be applied to the cell until it is erased below a maximum acceptable threshold voltage. Accordingly, if a flash cell has been erased, it will heavily conduct. In this case, the cell may be said to be storing a logic 1 (“ON cell”). Thus, by monitoring the bit line current, the programmed or erased state (i.e., 1 or 0) of the cell can be determined.
Meanwhile, most of the state-of-the-art flash memory devices of high density adopt a segmented cell array architecture in order to reduce the chip size. In a segmented array architecture, the bulk and the cells are divided into a number of sectors and the sources of the cells within a sector are commonly coupled to the corresponding bulk sector. This architecture causes all cells within a sector (of, e.g., 16 k or 64 k bytes capacity) to be erased simultaneously.
In such a sector erase operation, due to nonuniformity in the programmed threshold voltage, manufacturing condition, amount of use, temperature, etc., one or more cells within the sector may be erased below a minimum acceptable threshold voltage. This is because too much charge is removed from the floating gates of the cells, making the cells “depletion-like”. The cell erased below the minimum threshold is commonly referred to as being “overerased”. An overerased cell may induce a leakage current on its associated bit-line, thereby causing errors when reading other cells on the same bit-line. One solution to this problem is to repair the overerased cells. The method of repairing the overerased cells is an iterative process utilizing overerase verification and low-voltage level programming.
In general, the sector erase operation of flash EEPROM device is carried out as in the following. First, all of the cells within a sector are sequentially programmed to narrow their threshold distribution (referred to as “first programming”). All the cells of the sector are then erased simultaneously (referred to as “main erasing”). Thereafter, a repair operation begins by selecting a row of word-line and examining the cells on the selected row one by one along columns of bit-lines to determine whether any of the cells are overerased. This procedure is commonly referred to as overerase verification. In performing verification, a cell is identified as overerased when it conducts current in excess of the current expected at the lowest threshold voltage. Once identified as overerased, a cell is programmed using low-level repair voltages (e.g., 2-5 V to the control gate, 6-9 V to the drain, and 0 V to the source and bulk) (referred to as “second programming”). Repair of the remaining cells on other rows is performed in a similar fashion.
In such programming operations, the programmed threshold voltage of a flash cell is checked by a program verify algorithm. The program verification typically involves a series of interleaved program and read operations. In this verification operation, the amount of charge stored in the floating gate of the cell is monitored by supplying the selected word line with a program verify voltage (e.g., about 6 V), to determine if the cell has a desired threshold voltage. When the cell is programmed to the target threshold voltage (i.e., “program pass”), further programming of the cell is inhibited and programming of the next cell begins. If, however, the cell is identified as “program fail”, the cell is reprogrammed within the limit of a given maximum number of reprogramming operations.
In the above-described second programming operations, when a cell is identified as program fail, the main erasing and the second programming for the cell is performed again. An example of a contemporary technique for correcting overerased cells is described in U.S. Pat. No. 5,237,535 to Mielke et al., entitled “Method of Repairing Overerased Cells in a Flash Memory”.
FIG. 1
illustrates a conventional flash EEPROM device. The flash memory device includes a non-volatile EEPROM cell array
10
, a row decoder
12
, a word-line driving circuit
14
, a column decoder
16
, a column selector
18
, a voltage boosting circuit
20
, a voltage switching circuit
22
, and a program/erase control circuit
24
.
The voltage boosting circuit
20
generates the boosted voltage Vpp (e.g., 6-7 V) by using the power supply voltage (e.g., 2.7-3.6 V). The program/erase control circuit
24
generates a verify enable signal VER_EN which is activated for program verification and overerase verification in program and erase verify modes of the memory device. The voltage switching circuit
22
delivers either of the power supply voltage Vcc and the boosted voltage Vpp to the word-line driving circuit
14
in response to the verify enable signal VER_EN. As shown in
FIG. 1
, the word-line driving circuit
14
, placed between the row decoder
12
and the memory cell array
10
, consists of a plurality of word-line drivers WD
1
-WDm which correspond to the word-lines WL
1
-WLm, respectively.
Referring to
FIG. 2
, there is shown a detailed circuit configuration of the respective conventional word-line drivers WD
1
-WDm. As shown in the figure, each word-line driver WDi (i=1, 2, . . . , or m) includes a level shifter consisting of two P-channel MOS (PMOS) transistors
30
and
32
, two N-channel MOS (NMOS) transistors
34
and
36
, and an inverter
38
. The word-line driver (or level shifter) WDi is coupled to a corresponding word line WLi which is commonly coupled to the control gates of the memory cell transistors Ci
1
-Cin in the memory cell array
10
. The word-line driver WDi i

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