Pulse or digital communications – Bandwidth reduction or expansion – Television or motion video signal
Reexamination Certificate
1995-02-07
2001-05-22
Lee, Richard (Department: 2613)
Pulse or digital communications
Bandwidth reduction or expansion
Television or motion video signal
C348S714000, C375S240240
Reexamination Certificate
active
06236683
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to the field of digital image processing.
The sophistication and increased definition of displayed images, especially for high definition TV, has led to the development of various systems to, during transmission of moving images, transmit only a portion of these images, namely only the portion of the images which changes from one image to another.
FIG. 1
shows as exemplary general arrangement of a conventional TV image encoder. The encoder comprises a video signal input
1
, an analog-digital converter (ADC)
2
, a scanning system
3
for scanning images in blocks, a device for calculating the discrete cosine transform (DCT)
4
, a quantification system (Q)
5
, a varying length coding system (VLC)
6
, and a buffer memory
7
, the output of which is provided through a line
8
to the transmission channel or to an intermediate storing device (not shown). With the use of the cosine transform, the amount of information to be transmitted is reduced. In addition, a unit for comparing the current image with the previous image is provided. This system comprises devices for calculating reverse quantification (Q
−1
)
9
and reverse cosine transform (DCT
−1
)
10
, the results of which are provided to a frame memory
11
. Frame memory
11
contains, at a given time, the image preceding the current image. The content of this frame memory is compared by blocks to the content of the current image in a motion estimator
12
. Motion estimator
12
seeks, for each current image block, the portion of the preceding image most resembling the current image block. This most resembling portion is called the target portion and the distance between the current image block of interest and this target portion is called motion vector D. This vector constitutes a first input of a predictor
14
which also receives the preceding frame from frame memory
11
. The predictor output is sent back by an adder
15
into frame memory
11
. A subtracter
16
subtracts, from current image information, the information of the preceding image output from the frame memory and shifted by the predictor, block after block. The output of subtracter
16
is provided to the DCT calculating device
4
. Thus, at output
8
of the encoding system, one obtains a reduced amount of information, because the information has been subjected to two processings; the process for comparison with the preceding image and the cosine transform and quantification process. Hence, the bandwidth of the transmission channels is substantially decreased because less information needs to be transmitted.
FIG. 2
shows a decoder associated with the encoder of FIG.
1
. The decoder receives at its input
20
a signal corresponding to the transmitted signal
8
. This signal is processed by a variable length decoder (VLD)
21
, a system for calculating the reverse quantification
22
, and a system for calculating the reverse cosine transform
23
. The output of the system for calculating the reverse cosine transform is provided to a block to line scanning converter
25
, then to a digital/analog converter (DAC)
26
to provide a video signal
27
suitable, for example, to control a TV display system (not shown). In addition, the VLD system provides the motion vector D to a predictor
30
, which also receives the output of a frame memory
31
. The predictor output signal is added to the output of the circuit calculating the reverse cosine transform by an adder
32
. The output of adder
32
is provided, on the one hand, to the frame memory
31
and, on the other hand, to the scanning converter
25
.
The above description is intended only to exemplify an environment in which the invention can be applied. The invention specifically relates to the predictor
14
or
30
of the encoder or decoder; these predictors are of course identical, but for the sake of simplicity, the invention will be disclosed only in connection with the decoding circuit.
Up to now, the known predictors have been complex systems occupying a whole printed circuit board on which are arranged numerous components and especially numerous memories between which numerous interconnections are provided.
SUMMARY OF THE INVENTION
An object of the invention is to provide a predictor architecture which can be implemented in a single monolithic integrated circuit.
This object and other objects of the invention are achieved by providing a predictor intended to supply, in the form of a pixel block, an assembly of p target pixels of the preceding image so that each target pixel corresponds in the image to the adjacent pixels of the current pixel shifted by a predetermined motion vector. This predictor comprises a search memory having the size of a current column increased by maximum motions liable to be provided by the motion vector, each cell of this memory being independently addressable in read/write modes; three write decoders for simultaneously addressing in write mode three cells of three portions of the memory; p read decoders for simultaneously addressing in read mode p cells of p distinct sub-portions from the memory; and means for controlling the write decoders so that p successive write steps of data of the same nature corresponding to p adjacent points in the image are achieved in each p sub-portion.
REFERENCES:
patent: 4435835 (1984-03-01), Sakow et al.
patent: 4460923 (1984-07-01), Hirano et al.
patent: 4821119 (1989-04-01), Gharavi
patent: 4984070 (1991-01-01), Tanoka et al.
patent: 5142360 (1992-08-01), Niihara
patent: 5153720 (1992-10-01), Kawai
patent: 5162907 (1992-11-01), Keating et al.
patent: 5181229 (1993-01-01), Langlais et al.
patent: 5208667 (1993-05-01), Saunders
patent: 5210605 (1993-05-01), Zaccarin et al.
patent: 0363677 (1989-09-01), None
patent: 0363677 (1990-04-01), None
“IEEE Transactions on Circuits and Systems”, vol. 36, No. 10, Oct. 1989, New York, pp. 1267-1274.
“Signal Processing of HDTV, II”, Proceedings of the Third International Workshop on HDTV), Aug. 1989, Turin, Italy, pp. 273-283.
Harrand Michel
Mougeat Paul
Galanthay Theodore E.
Lee Richard
Morris James H.
SGS-Thomson Microelectronics S.A.
Wolf Greenfield & Sacks P.C.
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