Static information storage and retrieval – Floating gate – Multiple values
Reexamination Certificate
1999-01-12
2001-01-23
Tran, Andrew Q. (Department: 2824)
Static information storage and retrieval
Floating gate
Multiple values
C365S185200, C365S185210, C365S104000, C365S184000, C365S168000
Reexamination Certificate
active
06178114
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The field of the present invention relates to a multi-stage semiconductor memory and the sensing of multi-level memory cell data; and in particular to a method and apparatus for sensing multi-level cell data in one read cycle.
2. Description of Related Art
In a conventional memory cell, one bit of data is stored per cell. Popular classes of non-volatile semiconductor memory devices such as ROM and flash memory, have been modified to store more than one bit of data in one cell. This is accomplished by storing more than two threshold voltages V
t
either through different voltage threshold implantation for devices such as a MROM or by programming in devices such as flash cells.
A draw back to the MLC approach is that there is increased difficulty in sensing the various threshold voltages. This compromises the speed of reading the data. Also, since a more complicated sensing circuit is required additional chip area to implement the sense amplifier is required, increasing the cost of manufacturing a MLC.
Representative prior art sensing methods are described in U.S. Pat. No. 5,721,701 to Ikebe et al. entitled “HIGH READ SPEED MULTIVALUED READ ONLY MEMORY DEVICE”; and U.S. Pat. No. 5,543,738 to Lee et al. entitled “MULTI-STAGE SENSE AMPLIFIER FOR READ-ONLY MEMORY HAVING CURRENT COMPARATORS”. These approaches in the prior art for two bit per cell memory, require three word line voltage levels for sensing the four possible combinations of two bits. The three levels are achieved in one prior art approach by applying the three levels in a three step sequence to the word line in each read cycle, sensing the cell output for each of the three levels. This three step sequence is relatively slow. The three levels are achieved in another approach by a two step sequence applying a first fixed word line voltage, and followed by a lower word line voltage or a higher word line voltage depending on the outcome of sensing during the first step. The two step technique in the prior art overcomes the slowness of the three step technique, but adds complexity because of the logic required to control the word line voltage during the second step. Further, the two step sequences of the prior art is limited to a single order of sensing.
What is needed is a novel method and apparatus for fetching MLC data with a fixed word-line voltage for all bits in the MLC independent of the order in which the bits are sensed. What is also needed is a sensing circuit with reduced complexity and reduced cost.
SUMMARY OF THE INVENTION
Accordingly, the present invention is directed to a novel sensing method and apparatus to fetch multi-level cell (MLC) data using fixed word line voltages for both bits, or for all bits in the cell.
The present invention is directed to a novel sensing method and apparatus to sense multiple bits of data from a multi-level cell using fixed word line voltages for both bits, or for all bits in the cell. The sensing technique allows sensing a single bit from the cell, does not require any particular order of sensing of the multiple bits within a single cell, and has a sensing margin which is similar to prior art multi-level cell sense amplifiers.
Thus, the present invention provides a reading circuit for a multi-bit memory cell in a memory array. In a two bit per cell embodiment, the memory cell has a threshold gate voltage within a range of one of a first, second, third and fourth predetermined threshold voltages. These four predetermined threshold voltages correspond respectively to the four states of two-bits stored in the memory cell. A circuit to provide a gate voltage to the multi-bit memory cell during a read cycle is included. The gate voltage has a first level between the second and third predetermined threshold voltages during a first time interval of the read cycle for sensing one bit, for example the low bit, of the multi-bit data, and a second level between the third and fourth predetermined threshold voltages during a second time interval of the read cycle for sensing the next bit, that is the high bit in the cell. The grouping of the first and the second threshold voltages and the third and the fourth threshold voltages are also referred to as the low threshold voltage group and the high voltage threshold group, respectively, during the low bit cycle. During the high bit cycle the second and third threshold voltages and the first and the fourth voltage threshold groups are referred to as the inner and outer threshold voltage groups, respectively.
A sensing circuit in one embodiment is coupled to the multi-bit memory cell and compares the current from the multi-bit memory cell to a first reference current and a second reference current. The sensing circuit produces a first output during the first time interval having a first logic state when the current from the first cell exceeds the first reference current and a second logic state if the current from the cell is less than the first reference. The sensing circuit produces a second output during the second time interval having a first logic state if the current from the cell is less than the second reference current and greater than the first reference current, and a second logic state if the current from the cell is greater than the first reference current and less than the second reference current. The first and second outputs of the sensing circuit indicate the two bits stored in the multi-bit cell. The sensing method described above can be expanded to include MLCs having more than four threshold levels. As the number of threshold levels increase, additional current sources and logic circuits with corresponding logic states would be required to determine the data stored in the MLC.
According to one preferred aspect, the sensing circuit includes a first comparator connected to receive the first reference current and a current from the multi-bit memory cell, and a second comparator connected to receive the second reference current and current from the multi-bit memory cell. Logic is coupled to the first and second comparators and operates during the first time interval to provide the output of the first comparator as the first output, and operates during a second time interval to provide the output of the first comparator as the second output if the output of the second comparator has a first value, and to provide the output of the first comparator inverted as the second output if the output of the second comparator has a second value.
According to various aspects of the present invention, the first time interval for sensing may occur prior to the second time interval, or the first time interval may occur after the second time interval depending on the bit to be sensed, or the preferred implementation of the sensing circuit.
Also, the present invention provides a method for sensing a particular bit in a plurality of bits in a multi-bit cell that has a threshold gate voltage within a range of one of a plurality of predetermined threshold voltages which includes a highest, a next to highest and a lowest predetermined threshold voltage. The method involves applying a gate voltage to the multi-bit cell between the highest and the next to highest predetermined threshold voltages, and determining a first value for the bit if the current from the cell is less than a reference current indicating that the threshold gate voltage is the highest predetermined threshold voltage, or if the current from the cell is greater than a reference current indicating that the threshold gate voltage is the lowest predetermined threshold voltage. The method includes determining a second value for the bit if the current from the cell is greater than the first reference current and less than the second reference current indicating that the threshold gate voltage is one of the other predetermined threshold voltages in the plurality of predetermined threshold voltages.
When the plurality of bits in the multi-bit cell includes two bits, including the particular bit and another bit, the other bit is sensed by
Haynes Mark A.
Haynes & Beffel LLP
Macronix International Co. Ltd.
Tran Andrew Q.
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