Level-shifting circuit and input and output circuits using...

Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Current driver

Reexamination Certificate

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Details

C327S390000

Reexamination Certificate

active

06288580

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a level-shifting circuit which shifts a level of an input voltage, and input and output circuits using the level-shifting circuit.
2. Description of the Related Art
An example of a conventionally known level-shifting circuit is shown in FIG.
7
. This level-shifting circuit
1
comprises: an input terminal
2
; an n-channel type MOSFET N
5
which has its gate connected to the input terminal
2
and its drain connected to a voltage source V
DD
; a current source CS
1
which has its flow-in terminal connected to a source of the n-channel type MOSFET N
5
and its flow-out terminal connected to a ground potential; and an output terminal
6
which is connected at a interconnection point between the source of the n-channel type MOSFET N
5
and the flow-in terminal of the current source CS
1
.
The current source CS
1
through which a current I
DS
flows in this level-shifting circuit
1
is employed a constant-current source which is not affected by the manufacturing process, nor the operating temperature, nor the supply voltage.
The operations, explained next, of this level-shifting circuit are described with reference to FIG.
7
.
A gate-source voltage V
GS
of the n-channel type MOSFET N
5
when it is provided at its input terminal
2
with a high-level voltage V
IN
is given by the following Equation 1:
V
GS
={2
I
DS
/&bgr;}
½
+V
T
  1
where &bgr;=&mgr;C
OX
×W/L,
&mgr; is a surface mobility (m2/volt×second), COX is an electrostatic capacitance per unit area of gate channel (farad),
W
1
is a gate channel width (m) of the n-channel MOSFET N
1
, and
L
1
is a gate channel length (m) of the n-channel MOSFET N
1
.
An output voltage V
OUT
which appears at the output terminal
6
is given by:
V
OUT
=V
IN
−V
GS
  2
Substituting Equation 1 into Equation 2 yields:
V
OUT
=V
IN
−{2
I
DS
/&bgr;}
½
−V
T
  3
There is also provided a small-amplitude interface input circuit which uses this level-shifting circuit. An example of it is shown in FIG.
9
.
This small-amplitude interface input circuit
10
comprises: a differential amplifier circuit
12
; the level-shifting circuit
1
; and a comparator
14
. The level-shifting circuit
1
is formed together with the following-stage comparator
14
in the same chip, which comparator
14
is supplied with a supply voltage lower than a VDD for the level-shifting circuit
1
(e.g., 1.8V for the comparator
14
versus 3V for the level-shifting circuit), so that the level-shifting circuit
1
is used to shift the level of an input signal to such a range which can be received by the comparator
14
.
The differential amplifier circuit
12
comprises: input terminals
16
and
18
; a resistor R
3
, an n-channel type MOSFET N
3
which has its gate connected to the input terminal
16
and its drain connected via the resistor R
3
to the voltage source V
DD
; a resistor R
4
; an n-channel type MOSFET N
4
which has its gate connected to the input terminal
18
and its drain connected via the resistor R
4
to the voltage source V
DD
; and a current source
20
which has its flow-in terminal connected to sources of the n-channel type MOSFETs N
3
and N
4
and its flow-out terminal connected to the ground potential.
An output terminal O
4
of this differential amplifier circuit
12
(i.e., an interconnection point between the resistor R
4
and the source of the n-channel type MOSFET N
4
) is connected to a gate of an n-channel type MOSFET N
1
. The level-shifting circuit
1
has the same configuration as that shown in FIG.
7
. An output terminal
6
of the level-shifting circuit
1
is connected to an input (+) of the comparator
14
. To a reference input (−) of the comparator
14
is connected a voltage source (not shown) which supplies a reference voltage V
CP
. The comparator has its output connected to a CMOS internal circuit
22
.
The level-shifting circuit
1
acts to output to the comparator
14
such binary signals as corresponding to a binary value represented by two signals INA and INB (both of which are shown in
FIG. 10
) mutually opposite in phase and different in voltage level which are transmitted via a transmission line and received at the separate input terminals
16
and
18
of the differential amplifier circuit
12
.
That is, of the signals INA and INB (both of which are shown in
FIG. 10
) applied separately at the input terminals
16
and
18
respectively, the signal INB which is differential-amplified at the differential amplifier circuit
12
is supplied from the output terminal
04
of the differential amplifier circuit
12
to the level-shifting circuit
12
at its input terminal
2
, where the INB signal is shifted in level to such a signal V
OUT
1
(which is shown in
FIG. 10
) that can be received by the comparator
14
, and then output from the output terminal
6
of the level-shifting circuit
1
.
If the output signal V
OUT
1
is sequentially input as an idealistic signal having the reference voltage V
CP
as its center of amplitude as shown in
FIG. 10
as V
OUT
1
S of V
OUT
1
, since the reference voltage V
CP
is applied to the comparator at its reference input (−), the comparator
14
sequentially outputs a binary signal having such a waveform as V
OUT
2
(
1
) in
FIG. 10
, which signal is then processed in the CMOS internal circuit
22
.
Therefore, that signal processing has no inconvenience at all.
Also, an example of the small-amplitude interface input circuit is shown in FIG.
11
.
This small-amplitude interface input circuit
30
comprises: a differential amplifier circuit
32
; a level-shifting circuit
34
; and a differential amplifier circuit
36
, in such a configuration that the level-shifting circuit
34
has two level-shifting circuits, each of which has the same configuration as that shown in
FIG. 7
, connected separately to the output terminals O
3
and O
4
of the differential amplifier circuit
32
. The differential amplifier circuit
32
has the same configuration as that shown in FIG.
9
. The level-shifting circuit
34
is configured of two level-shifting circuits each of which is shown in
FIG. 7
, in such a way that a first level-shifting circuit
34
1
consists of an n-channel type MOSFET N
1
and a constant current source CS
1
1
, while a second level-shifting circuit
34
2
consists of an n-channel type MOSFET N
2
and a constant current source CS
1
2
.
With this, the level-shifting circuit is formed together with the following-stage differential amplifier circuit
36
in the same chip, which differential amplifier circuit
36
is supplied with a V
DD
lower than a voltage source for the level-shifting circuit
34
(e.g., 1.8V for the differential amplifier circuit
36
versus 3V for the level-shifting circuit
34
), so that the level-shifting circuit
34
is used to shift a signal supplied to the differential amplifier circuit
36
to such a range of level that can be received by the differential amplifier circuit
36
. The reason why the level-shifting circuit
34
is used in this small-amplitude interface input circuit
30
is that if the differential amplifier circuit
36
connected at the stage following the level-shifting circuit
34
is supplied with a signal having a potential of the voltage source V
DD
or higher (e.g., if a signal having 2.5V as its signal amplitude center as against V
DD
=1.8V is supplied via a bus line), it is rendered inoperative, so that to prevent such an event from occurring, a level of signals supplied to the differential amplifier circuit
36
must be shifted to such a range of level that can be received by the differential amplifier circuit
36
.
Like that shown in
FIG. 9
, this small-amplitude interface input circuit
30
also causes the differential amplifier circuit
36
to output binary signals which correspond to binary values represented by two signals INA and INB mutually opposite in phase and different in voltage level which

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