Shallow trench isolation method of a semiconductor wafer

Details Shallow trench isolation method of a semiconductor wafer Shallow trench isolation method of a semiconductor wafer

1998-11-11

2001-04-17

Fourson, George (Department: 2823)

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Grooved and refilled with deposited dielectric material

C438S437000, C438S692000, C438S699000

Reexamination Certificate

active

06218267

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a shallow trench isolation method of a semiconductor wafer.
2. Description of the Prior Art
Typically, the localized oxidation isolation (LOCOS) method is used for isolating many MOS transistors on a semiconductor wafer to prevent inter-component disturbances or short-circuiting. Using the LOCOS method of oxidizing the silicon substrate at high temperatures, a SiO2 layer (field oxide layer) with several thousand angstroms of distance between two transistor components is generated. However, pits, crystal defects or a bird's beak deformity may form to negatively affect the semiconductor wafer characteristics. The larger volume of the SiO2 layer will affect the integration of the whole semiconductor wafer.
At present, the most commonly used isolation method for isolating MOS transistors in semiconductor processing less than 0.25 &mgr;m is shallow trench isolation. Although this method effectively achieves electrical isolation by filling dielectric material in the shallow trench between any two neighboring components within the semiconductor wafer, there is still a possibility of the dishing phenomenon occurring on the surface of shallow trench. This may affect the electrical performance of the semiconductor wafer. Please refer to
FIGS. 1
to
6
.
FIGS. 1
to
6
show the prior art shallow trench isolation method for a semiconductor wafer.
As shown in
FIG. 1
, a plurality of shallow trenches
12
are formed on the surface of a semiconductor wafer
10
by performing photolithography and etching. The semiconductor wafer
10
comprises a Si substrate
14
, a pad oxide layer
16
composed of SiO2 formed over the Si substrate
14
, and a pad nitride layer
18
composed of Si3N4 deposited over the pad oxide layer
16
. The pad oxide layer
16
and pad nitride layer
18
are used as masks or sacrificial layers during ion implantation or heat diffusion.
A Si(OC2H5)4 (tetra-ethyl-ortho-silicate TEOS) layer and a Poly-Silicon layer are deposited in the proper sequence by performing chemical vapor deposition (CVD). As shown in
FIG. 2
, a TEOS layer
20
evenly covers the surface of the semiconductor wafer
10
and is used as a dielectric layer, and a Poly-Silicon layer
22
is used as a mask.
The unnecessary parts of the Poly-Silicon layer
22
are stripped and the surface of the semiconductor wafer
10
is polished by performing chemical-mechanical polishing (CMP). As shown in
FIG. 3
, the Poly-Silicon
24
in the corresponding dishes above the shallow trenches
12
remains, and the surface of the semiconductor wafer
10
is flat.
The remaining Poly-Silicon
24
and TEOS layer
20
are etched on the surface of the semiconductor wafer
10
by performing reactive ion etching or magnetically enhanced reactive ion etching. Please refer to FIG.
4
. When reactive ion etching is performed, the remaining Poly-Silicon
24
will function as a mask above the shallow trench
12
. Therefore, after etching, several remaining overhangs
26
are formed above the shallow trenches
12
. The remaining TEOS layer
20
and several overhangs
26
are tightened by annealing the semiconductor wafer
10
.
Afterwards, the remaining overhangs
26
will be eliminated and the surface of the semiconductor wafer
10
will be polished by performing CMP. As shown in
FIG. 5
, the surface of the semiconductor wafer
10
is flat. The pad oxide layer
16
and pad nitride layer
18
on the surface of the semiconductor wafer
10
are then stripped. As shown in
FIG. 6
, only Si substrate
14
and several shallow trenches
12
comprising TEOS are left on the surface of semiconductor wafer
10
.
When performing the CMP and back etching techniques as shown in FIG.
5
and
FIG. 6
, the surface of TEOS in the shallow trench
12
is etched and a dish
28
is generated. The wider the surface, the more serious the dishing problem. Dishing affects the semiconductor wafer
10
electrically during film layer deposition and causes focusing problems when transferring patterns.
SUMMARY OF THE INVENTION
It is therefore a primary objective of the present invention to provide a shallow trench isolation method of a semiconductor wafer where dishing does not occur to solve the above mentioned problem.
In a preferred embodiment, the present invention relates to a method for electrically isolating shallow trenches between components on the surface of a semiconductor wafer comprising:
(1) covering the surface of the semiconductor wafer with the dielectric material to form a first dielectric layer, filling each shallow trench on the surface of the semiconductor wafer and the corresponding dish above each shallow trench with dielectric material;
(2) depositing a second dielectric layer in each dish of the first dielectric layer;
(3) polishing the surface of the semiconductor wafer to strip off the second dielectric layer in each dish of the first dielectric layer and cutting the surface of dielectric material in each shallow trench and on each component on the surface of the semiconductor wafer.
It is an advantage of the present invention that dishing is avoided so the semiconductor wafer will not be affected electrically and focusing problems when transferring patterns will not occur.
These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment which is illustrated in the various figures and drawings.


REFERENCES:
patent: 5661073 (1997-08-01), Jeng
patent: 5930646 (1999-07-01), Gerung et al.
patent: 6037237 (2000-03-01), Park et al.

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