Electricity: electrical systems and devices – Safety and protection of systems and devices – With specific quantity comparison means
Reexamination Certificate
1999-05-21
2001-09-18
Sherry, Michael J. (Department: 2836)
Electricity: electrical systems and devices
Safety and protection of systems and devices
With specific quantity comparison means
C361S091100, C361S091200, C361S091500, C324S763010
Reexamination Certificate
active
06292342
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to a voltage protection circuit for a semiconductor test system, and more particularly, to a voltage protection circuit for a semiconductor test system which functions both as an excessive voltage clamp detection circuit and an abnormal voltage detection circuit with small number of components and low cost.
BACKGROUND OF THE INVENTION
In testing a semiconductor integrated circuit device by a semiconductor test system, the semiconductor IC device to be tested (device under test or DUT) is provided with test signals and the resultant output signals of the device under test are compared with expected value signals prepared in advance to determine whether the intended functions of the device under test is performed correctly.
Such a test signal is supplied to each pin of the device under test from a driver circuit via a transmission cable. The driver circuit functions as a buffer amplifier whereby providing a predetermined amplitude to the test signal. The resultant output signal of the device under test is compared with the expected value by a comparator. A large number of sets of driver circuits and comparators are assembled in a pin electronics unit in the semiconductor test system. To protect both the driver circuit and comparator as well as the device under test from excessive voltages caused by various factors, a voltage protection circuit is usually provided in connection with the driver circuit and comparator.
An example of conventional circuit diagram of a voltage protection circuit in a semiconductor test system is shown in FIG.
2
. This example shows that the protection circuit is employed at the connection point between the comparator and the transmission cable (output of DUT). In this example, the protection circuit functions as both an excessive voltage clamp circuit and an abnormal voltage detection circuit. The operation of the circuit arrangement of
FIG. 2
is explained with reference to
FIGS. 2-5
.
In the conventional example of
FIG. 2
, the main portion of the excessive voltage clamp circuit and the abnormal voltage detection circuit includes diodes D
1
-D
8
, buffer amplifiers OP
1
-OP
4
, comparators CP
1
and CP
2
, and switches SW
1
, SW
4
and SW
5
. A comparator
90
is provided to compare the output signal of the DUT which is resulted from a test signal provided to the DUT through a driver (not shown). Similar protection circuit can be arranged at the output of the driver circuit.
The excessive voltage clamp circuit clamps an excessive voltage in the output voltage of the DUT. The abnormal voltage detection circuit detects an abnormal voltage which is larger than the excessive voltage and opens the switch SW
1
to disconnect the comparator
90
from the DUT.
First, the operation of the excessive voltage clamp circuit is explained. The excessive voltage clamp circuit comprises the diodes D
3
, D
4
, D
7
and D
8
, the buffer amplifiers OP
1
and OP
2
, and switches SW
1
, SW
4
and SW
5
.
The switch SW
1
remains closed (ON) when the clamping operation is performed. Also, the switches SW
4
and SWS remain closed (ON) when clamping operation on the output voltage from the DUT is performed.
The operation of the clamp circuit is explained with reference to a simplified circuit diagram of FIG.
3
. In
FIG. 3
, only fundamental components are shown while omitting the buffer amplifiers OP
1
and OP
2
and diodes D
3
and D
4
therefrom for simplicity of explanation. The switches SW
4
, SW
5
are turned on when the clamping operation is carried out and are turned off when the clamping operation for the output voltage of the DUT is not performed.
Thus, in
FIG. 3
, the excess voltage clamp circuit is basically configured by the switches SW
4
and SW
5
and the diodes D
7
and D
8
. The connection point of the diodes D
7
and D
8
is commonly connected to the input of the comparator
90
which receives the output signal of the DUT through the transmission cable
200
. Clamp voltages VH and VL in
FIG. 2
are set to define the high level clamp voltage and the low level clamp voltage, respectively.
FIG.
4
(
a
) shows an example of a voltage waveform when the output of the DUT through the transmission cable
200
is not clamped. As noted above, generally, a device under test (DUT) has a plurality of terminal pins, and each terminal pin is connected to the pin electronics unit having a comparator and a driver circuit, etc., through a corresponding transmission cable
200
.
The transmission line
200
is so structured to have a characteristic (transmission) impedance, which is for example, 50 ohms. The impedance of the transmission cable is designed to match with the impedance of the terminal pin of the DUT to achieve an accurate test result in a high frequency range. However, a semiconductor test system needs to test various types of DUTs, and thus, the output impedance at a terminal pin of a DUT does not necessarily match with the impedance of the transmission cable.
For example, when the output impedance of the DUT is smaller than the impedance of the load (input of the comparator
90
), a reflection waveform is superimposed on the transmission signal as shown in FIG.
4
(
a
). In such a case, the testing on the DUT cannot be properly performed because the output voltage of the DUT received by the comparator
90
may exceed the voltage limit of the comparator
90
or include incorrect representation of the actual DUT output signal, thereby causing a breakdown or resulting in a measurement error in the test result.
Therefore, a semiconductor test system includes a voltage protection circuit such as shown in
FIG. 2
to limit the output voltage of the DUT by establishing an upper clamp voltage and a lower clamp voltage. For example, when a DUT is a TTL IC, an upper clamp voltage VH of 5V and a lower clamp voltage VL of 0V for low voltage VL will be established in the excess voltage clamp circuit.
In
FIG. 3
, assuming a forward bias voltage of each of the diodes D
7
and D
8
is Vf. As is well known in the art, such a forward bias voltage of a silicon diode is 0.7V. Thus, in the case where the clamp voltages VH and VL are 5V and 0V, for example, the diode D
8
turns on when the output of the DUT becomes higher than 5V+Vf. Consequently, the voltage at the input of the comparator
90
is limited to the voltage level of 5V+Vf by flowing a current from the DUT to the clamp voltage VH through the diode D
8
. Conversely, the diode D
7
turns on when the output of the DUT becomes lower than 0V−Vf, thereby limiting the input voltage of the comparator
90
to the voltage level of 0V−Vf while allowing the current flow from the clamp voltage VL to the DUT. As a result, the output voltage of the DUT is clamped to limit the excessive voltage as shown by the voltage waveform of FIG.
4
(
b
).
In the basic operation involved in the configuration of
FIG. 3
, there arises a potential difference of Vf in the actually clamped voltage from the intended clamp voltage VH or VL because of the forward bias voltage of the diodes D
7
and D
8
. In order to avoid the effect of the forward bias voltage Vf in the foregoing, the protection circuit of
FIG. 2
is designed to compensate the voltage difference by canceling the bias voltage Vf of each of the diodes D
7
and D
8
. Such a function is performed by using a set of a buffer amplifier OP
1
and a diode D
3
and a set of a buffer amplifier OP
2
and a diode D
4
. Each of the buffer amplifiers OP
1
and OP
2
functions as a voltage follower.
A constant current source A
3
provides a bias current to the diode D
3
to produce a forward bias voltage Vf in the diode D
3
. Similarly, a constant current source A
4
provides a bias current to the diode D
4
to produce a forward bias voltage Vf in the diode D
4
. Under this arrangement, the voltage at the anode of the diode D
7
becomes VL+Vf and the cathode of the diode D
8
becomes VH−Vf. Hence, the actually clamped voltage in the output of the DUT is equal to the upper clamp voltage VH or the lower clamp voltage V
Advantest Corp.
Muramatsu & Associates
Sherry Michael J.
LandOfFree
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